AMC7812 datasheet(33/92 Pages) TI

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AMC7812

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SBAS513D – JANUARY 2011 – REVISED OCTOBER 2012

ADC Data Format

For a single ended input, the conversion result is stored in straight binary format. For a differential input, the

results are stored in twos complement format.

SCLK Clock Noise Reduction

To avoid noise caused by the bus clock, it is recommended that no bus clock activity occurs for at least the

conversion process time immediately after the ADC conversion starts.

Programmable Conversion Rate

The maximum conversion rate is 500kSPS for a single channel in auto mode, as shown in Table 1. The

conversion rate is programmable through the CONV-RATE-[1:0] bits of AMC Configuration Register 1. When

more than one channel is selected, the conversion rate is divided by the number of channels selected in ADC

Channel Register 0 and ADC Channel Register 1. In auto mode, the CONV-RATE-[1:0] bits determine the actual

conversion rate. In direct mode, the CONV-RATE-[1:0] bits limit the maximum possible conversion rate. The

actual conversion rate in direct mode is determined by the rate of the conversion trigger. Note that when a trigger

is issued, there may be a delay of up to 4µs to internally synchronize and initiate the start of the sequential

channel conversion process. In both direct and auto modes, when the CONV-RATE-[1:0] bits are set to a value

other than the maximum rate ('00'), nap mode is activated between conversions. By activating nap mode, the

AIDD supply current is reduced, as shown in Figure 67.

Table 1. ADC Conversion Rate

tACQ

tCONV

NAP

THROUGHPUT

CONV-RATE-1

CONV-RATE-0

(µs)

ENABLED

(Single-Channel Auto Mode)

0.375

1.625

500kSPS (default)

2.375

1.625

Yes

250kSPS

6.375

1.625

Yes

125kSPS

14.375

1.625

Yes

62.5kSPS

Handshaking with the Host (see AMC Configuration Register 0)

The DAV pin and the DAVF (data available flag) bit in AMC Configuration Register 0 provide handshaking with

the host. Pin and bit status depend on the conversion mode (direct or auto), as shown in Figure 84 and

Figure 85. In direct mode, after ADC-n-Data Registers of all of the selected channels are updated, the DAVF bit

in AMC Configuration Register 0 is set immediately to '1', and the DAV pin is active (low) to signify that new data

are available. Reading the ADC-n-Data Register or restarting via the external CNVT pin, the ADC clears the

DAVF bit to '0' and deactivates the DAV pin (high). If an internal convert start (ICONV bit) is used to start the new

ADC conversion, in order to reset the DAV status, an ADC-n-Data Register must be read after the current

conversion finishes before a new conversion can be started.

In auto-mode, after the ADC-n-Data Registers of the selected channels are updated, a pulse of 1µs (low)

appears on the DAV pin to signify that new data are available. However, the DAVF bit is always cleared to '0' in

auto-mode.

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