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EP3SL340 Datasheet(PDF) 241 Page - Altera Corporation

Part # EP3SL340
Description  Stratix III Device Handbook
PDF  341 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3SL340 Datasheet(HTML) 241 Page - Altera Corporation

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
1–231
I/O Timing
© July 2010
Altera Corporation
Stratix III Device Handbook, Volume 2
Table 1–112 lists the EP3SE80 row pins input timing parameters for single-ended I/O
standards.
1.2-V HSTL
CLASS I
GCLK
t
su
-0.974
-0.974
-1.401 -1.520 -1.642 -1.587 -1.944 -1.520 -1.642 -1.587 -1.944
ns
t
h
1.117
1.117
1.599
1.742
1.884
1.817
2.175
1.742
1.884
1.817
2.175
ns
GCLK
PLL
t
su
-1.227
-1.227
-1.766 -1.912 -2.091 -1.982 -2.432 -1.912 -2.091 -1.982 -2.432
ns
t
h
1.527
1.527
2.197
2.394
2.625
2.488
2.952
2.394
2.625
2.488
2.952
ns
1.2-V HSTL
CLASS II
GCLK
t
su
-0.962
-0.962
-1.391 -1.509 -1.626 -1.571 -1.928 -1.509 -1.626 -1.571 -1.928
ns
t
h
1.105
1.105
1.589
1.731
1.868
1.801
2.159
1.731
1.868
1.801
2.159
ns
GCLK
PLL
t
su
-1.215
-1.215
-1.756 -1.901 -2.075 -1.966 -2.416 -1.901 -2.075 -1.966 -2.416
ns
t
h
1.515
1.515
2.187
2.383
2.609
2.472
2.936
2.383
2.609
2.472
2.936
ns
3.0-V PCI
GCLK
t
su
-0.962
-0.962
-1.391 -1.509 -1.626 -1.571 -1.928 -1.509 -1.626 -1.571 -1.928
ns
t
h
1.105
1.105
1.589
1.731
1.868
1.801
2.159
1.731
1.868
1.801
2.159
ns
GCLK
PLL
t
su
-1.215
-1.215
-1.756 -1.901 -2.075 -1.966 -2.416 -1.901 -2.075 -1.966 -2.416
ns
t
h
1.515
1.515
2.187
2.383
2.609
2.472
2.936
2.383
2.609
2.472
2.936
ns
3.0-V PCI-X
GCLK
t
su
-1.065
-1.065
-1.504 -1.638 -1.871 -1.818 -2.172 -1.638 -1.871 -1.818 -2.172
ns
t
h
1.206
1.206
1.703
1.863
2.116
2.049
2.408
1.863
2.116
2.049
2.408
ns
GCLK
PLL
t
su
-1.318
-1.318
-1.869 -2.030 -2.320 -2.213 -2.660 -2.030 -2.320 -2.213 -2.660
ns
t
h
1.616
1.616
2.301
2.515
2.857
2.720
3.185
2.515
2.857
2.720
3.185
ns
Table 1–111. EP3SE80 Column Pins Input Timing Parameters (Part 3 of 3)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
Table 1–112. EP3SE80 Row Pins Input Timing Parameters (Part 1 of 3)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
3.3-V LVTTL
GCLK
t
su
-0.922
-0.964
-1.369 -1.481 -1.595 -1.647 -1.890 -1.492 -1.697 -1.649 -1.929
ns
t
h
1.045
1.103
1.566
1.703
1.842
1.878
2.128
1.725
1.950
1.890
2.168
ns
GCLK
PLL
t
su
1.087
1.110
1.770
2.000
1.985
2.004
1.799
2.012
2.003
2.024
1.850
ns
t
h
-0.825
-0.830
-1.353 -1.532 -1.470 -1.513 -1.300 -1.533 -1.477 -1.523 -1.349
ns
3.3-V
LVCMOS
GCLK
t
su
-0.922
-0.964
-1.369 -1.481 -1.595 -1.647 -1.890 -1.492 -1.697 -1.649 -1.929
ns
t
h
1.045
1.103
1.566
1.703
1.842
1.878
2.128
1.725
1.950
1.890
2.168
ns
GCLK
PLL
t
su
1.087
1.110
1.770
2.000
1.985
2.004
1.799
2.012
2.003
2.024
1.850
ns
t
h
-0.825
-0.830
-1.353 -1.532 -1.470 -1.513 -1.300 -1.533 -1.477 -1.523 -1.349
ns
3.0-V LVTTL
GCLK
t
su
-0.928
-0.975
-1.366 -1.482 -1.598 -1.650 -1.893 -1.491 -1.702 -1.654 -1.934
ns
t
h
1.051
1.114
1.563
1.704
1.845
1.881
2.131
1.724
1.955
1.895
2.173
ns
GCLK
PLL
t
su
1.081
1.099
1.773
1.999
1.982
2.001
1.796
2.013
1.998
2.019
1.845
ns
t
h
-0.819
-0.819
-1.356 -1.531 -1.467 -1.510 -1.297 -1.534 -1.472 -1.518 -1.344
ns



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