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EP3SL340 Datasheet(PDF) 270 Page - Altera Corporation

Part # EP3SL340
Description  Stratix III Device Handbook
PDF  341 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3SL340 Datasheet(HTML) 270 Page - Altera Corporation

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Stratix III Device Handbook, Volume 2
© July 2010
Altera Corporation
1.5-V HSTL
CLASS I
GCLK
t
su
-0.877
-0.931
-1.300 -1.400 -1.506 -1.454 -1.793 -1.406 -1.513 -1.462 -1.836
ns
t
h
1.002
1.071
1.498
1.621
1.747
1.684
2.024
1.636
1.761
1.702
2.068
ns
GCLK
PLL
t
su
1.150
1.165
1.857
2.097
2.198
2.211
2.147
2.113
2.210
2.093
2.194
ns
t
h
-0.887
-0.884
-1.439 -1.631 -1.685 -1.722 -1.650 -1.638 -1.687 -1.598 -1.693
ns
1.5-V HSTL
CLASS II
GCLK
t
su
-0.877
-0.931
-1.300 -1.400 -1.506 -1.454 -1.793 -1.406 -1.513 -1.462 -1.836
ns
t
h
1.002
1.071
1.498
1.621
1.747
1.684
2.024
1.636
1.761
1.702
2.068
ns
GCLK
PLL
t
su
1.150
1.165
1.857
2.097
2.198
2.211
2.147
2.113
2.210
2.093
2.194
ns
t
h
-0.887
-0.884
-1.439 -1.631 -1.685 -1.722 -1.650 -1.638 -1.687 -1.598 -1.693
ns
1.2-V HSTL
CLASS I
GCLK
t
su
-0.868
-0.919
-1.291 -1.390 -1.490 -1.438 -1.777 -1.397 -1.497 -1.446 -1.820
ns
t
h
0.993
1.059
1.489
1.611
1.731
1.668
2.008
1.627
1.745
1.686
2.052
ns
GCLK
PLL
t
su
1.159
1.177
1.866
2.107
2.214
2.227
2.163
2.122
2.226
2.109
2.210
ns
t
h
-0.896
-0.896
-1.448 -1.641 -1.701 -1.738 -1.666 -1.647 -1.703 -1.614 -1.709
ns
1.2-V HSTL
CLASS II
GCLK
t
su
-0.868
-0.919
-1.291 -1.390 -1.490 -1.438 -1.777 -1.397 -1.497 -1.446 -1.820
ns
t
h
0.993
1.059
1.489
1.611
1.731
1.668
2.008
1.627
1.745
1.686
2.052
ns
GCLK
PLL
t
su
1.159
1.177
1.866
2.107
2.214
2.227
2.163
2.122
2.226
2.109
2.210
ns
t
h
-0.896
-0.896
-1.448 -1.641 -1.701 -1.738 -1.666 -1.647 -1.703 -1.614 -1.709
ns
3.0-V PCI
GCLK
t
su
-0.923
-0.971
-1.361 -1.477 -1.739 -1.645 -2.029 -1.487 -1.742 -1.688 -2.069
ns
t
h
1.047
1.110
1.558
1.699
1.981
1.876
2.264
1.719
1.994
1.927
2.305
ns
GCLK
PLL
t
su
1.016
0.989
1.635
1.850
1.961
1.890
1.805
1.902
1.977
1.859
1.854
ns
t
h
-0.756
-0.711
-1.221 -1.385 -1.446 -1.403 -1.306 -1.427 -1.451 -1.363 -1.352
ns
3.0-V
PCI-X
GCLK
t
su
-0.923
-0.971
-1.361 -1.477 -1.739 -1.645 -2.029 -1.487 -1.742 -1.688 -2.069
ns
t
h
1.047
1.110
1.558
1.699
1.981
1.876
2.264
1.719
1.994
1.927
2.305
ns
GCLK
PLL
t
su
1.016
0.989
1.635
1.850
1.961
1.890
1.805
1.902
1.977
1.859
1.854
ns
t
h
-0.756
-0.711
-1.221 -1.385 -1.446 -1.403 -1.306 -1.427 -1.451 -1.363 -1.352
ns
Table 1–122. EP3SE110 Row Pins Input Timing Parameters (Part 3 of 3)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V



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