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EP3SL340 Datasheet(PDF) 335 Page - Altera Corporation |
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EP3SL340 Datasheet(HTML) 335 Page - Altera Corporation |
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335 / 341 page ![]() Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics 1–325 I/O Timing © July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 Table 1–200 and Table 1–201 list the periphery clock timing parameters for EP3SE260 devices. Table 1–200. EP3SE260 Column Pin Periphery Clock Timing Specifications Parameter Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V t CIN 1.709 1.716 2.620 2.765 3.177 3.039 3.668 2.765 3.177 3.039 3.668 ns t COUT 1.709 1.716 2.620 2.765 3.177 3.039 3.668 2.765 3.177 3.039 3.668 ns t PLLCIN 0.037 0.037 -0.202 -0.213 -0.140 -0.119 0.075 -0.213 0.293 -0.119 0.075 ns t PLLCOUT 0.037 0.037 -0.202 -0.213 -0.140 -0.119 0.075 -0.213 0.293 -0.119 0.075 ns Table 1–201. EP3SE260 Row Pin Periphery Clock Timing Specifications Parameter Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V t CIN 1.495 1.574 2.378 2.518 2.878 2.776 3.072 2.555 2.926 2.776 3.072 ns t COUT 1.413 1.483 2.223 2.355 2.697 2.605 2.913 2.385 2.737 2.605 2.913 ns t PLLCIN 0.065 0.172 -0.084 -0.118 -0.103 -0.033 -0.071 -0.103 0.384 -0.033 -0.071 ns t PLLCOUT -0.017 0.081 -0.236 -0.281 -0.284 -0.204 -0.230 -0.273 0.195 -0.204 -0.230 ns |
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