ISP1507CBS datasheet(9/74 Pages) NXP

9 / 74 page

ISP1507C_ISP1507D_1

Product data sheet

Rev. 01 — 28 May 2008

9 of 74

NXP Semiconductors

ISP1507C; ISP1507D

ULPI HS USB host and peripheral transceiver

While it is possible for the external 5 V supply to use the ISP1507 internal A_VBUS_VLD

comparator, typical 5 V supplies must provide their own power fault indicator that can be

connected as an input to the ISP1507 FAULT pin.

7.6.2 Session valid comparator

The session valid comparator is a TTL-level input that determines when VBUS is high

enough for a session to start. Peripherals, A-devices and B-devices use this comparator to

detect when a session is started. The A-device also uses this comparator to determine

when a session is completed. The session valid threshold of the ISP1507 is VB_SESS_VLD,

with a hysteresis of Vhys(B_SESS_VLD).

7.6.3 Session end comparator

The ISP1507 session end comparator determines when VBUS is below the B-device

session end threshold. The B-device uses this threshold to determine when a session has

ended. The session end threshold of the ISP1507 is VB_SESS_END.

7.7 SRP charge and discharge resistors

The ISP1507 provides on-chip resistors for short-term charging and discharging of VBUS.

These are used by the B-device to request a session, prompting the A-device to restore

the VBUS power. First, the B-device makes sure that VBUS is fully discharged from the

previous session by setting the DISCHRG_VBUS register bit to logic 1 and waiting for

SESS_END to be logic 1. Then the B-device charges VBUS by setting the CHRG_VBUS

threshold and starts a session by turning on the VBUS power.

7.8 Band gap reference voltage

The band gap circuit provides a stable internal voltage reference to bias the analog

circuitry. The band gap requires an accurate external reference resistor, RRREF, connected

between the RREF and GND pins. For details, see Section 16.

7.9 Power-on reset

The ISP1507 has an internal power-on reset circuit that resets all internal logic on

power-up. The ULPI is also reset at power-up.

Remark: When CLOCK starts toggling after power-up, the USB link must issue a reset

command over the ULPI bus to ensure correct operation of the ISP1507.

7.10 Detailed description of pins

7.10.1 DATA[7:0]

The ISP1507 is a Physical layer (PHY) containing a USB transceiver. DATA[7:0] is a

bidirectional data bus. The USB link must drive DATA[7:0] to LOW when the ULPI bus is

idle. When the link has data to transmit to the PHY, it drives a nonzero value.

Weak pull-down resistors are incorporated into DATA[7:0] pins as part of the interface

protect feature. For details, see Section 9.3.1.

The data bus can be reconﬁgured to carry various data types, as given in Section 8 and

Section 9.

ISP1507CBS Datasheet(PDF) 9 Page - NXP Semiconductors

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