AM79C973VCW datasheet(30/304 Pages) AMD

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Am79C973/Am79C975

P R E L I M INARY

INTA

Interrupt Request

Output

An attention signal which indicates that one or more of

the following status flags is set: EXDINT, IDON, MERR,

MISS, MFCO, MPINT, RCVCCO, RINT, SINT, TINT,

TXSTRT, UINT, MCCINT, MPDTINT, MAPINT, MRE-

INT, and STINT. Each status flag has either a mask or

an enable bit which allows for suppression of INTA as-

sertion. Table 1 shows the flag descriptions. By default

INTA is an open-drain output. For applications that

need a high-active edge-sensitive interrupt signal, the

INTA pin can be configured for this mode by setting IN-

TLEVEL (BCR2, bit 7) to 1.

When RST is active, INTA is the output for NAND tree

testing.

IRDY

Initiator Ready

Input/Output

IRDY indicates the ability of the initiator of the transac-

tion to complete the current data phase. IRDY is used

in conjunction with TRDY. Wait states are inserted until

both IRDY and TRDY are asserted simultaneously. A

data phase is completed on any clock when both IRDY

and TRDY are asserted.

When the Am79C973/Am79C975 controller is a bus

master, it asserts IRDY during all write data phases to

indicate that valid data is present on AD[31:0]. During

all read data phases, the device asserts IRDY to indi-

cate that it is ready to accept the data.

When the Am79C973/Am79C975 controller is the tar-

get of a transaction, it checks IRDY during all write data

phases to determine if valid data is present on

AD[31:0]. During all read data phases, the device

checks IRDY to determine if the initiator is ready to ac-

cept the data.

When RST is active, IRDY is an input for NAND tree

testing.

PAR

Parity

Input/Output

Parity is even parity across AD[31:0] and C/BE[3:0].

When the Am79C973/Am79C975 controller is a bus

master, it generates parity during the address and write

data phases. It checks parity during read data phases.

When the Am79C973/Am79C975 controller operates

in slave mode, it checks parity during every address

phase. When it is the target of a cycle, it checks parity

during write data phases and it generates parity during

read data phases.

When RST is active, PAR is an input for NAND tree

testing.

PERR

Parity Error

Input/Output

During any slave write transaction and any master read

transaction, the Am79C973/Am79C975 controller as-

serts PERR when it detects a data parity error and re-

porting of the error is enabled by setting PERREN (PCI

Command register, bit 6) to 1. During any master write

transaction, the Am79C973/Am79C975 controller

monitors PERR to see if the target reports a data parity

error.

When RST is active, PERR is an input for NAND tree

testing.

Table 1. Interrupt Flags

Name

Description

Mask Bit

Interrupt Bit

EXDINT

Excessive

Deferral

CSR5, bit 6

CSR5, bit 7

IDON

Initialization

Done

CSR3, bit 8

CSR0, bit 8

MERR

Memory Error

CSR3, bit 11

CSR0, bit 11

MISS

Missed Frame

CSR3, bit 12

CSR0, bit 12

MFCO

Missed Frame

Count Over-

flow

CSR4, bit 8

CSR4, bit 9

MPINT

Magic Packet

Interrupt

CSR5, bit 3

CSR5, bit 4

RCVCCO

Receive

Collision Count

Overflow

CSR4, bit 4

CSR4, bit 5

RINT

Receive

Interrupt

CSR3, bit 10

CSR0, bit 10

SINT

System Error

CSR5, bit 10

CSR5, bit 11

TINT

Transmit

Interrupt

CSR3, bit 9

CSR0, bit 9

TXSTRT

Transmit Start

CSR4, bit 2

CSR4, bit 3

UINT

User Interrupt

CSR4, bit 7

CSR4, bit 6

MCCINT

MII

Management

Command

Complete

Interrupt

CSR7, bit 4

CSR7, bit 5

MPDTINT

MII PHY Detect

Transition

Interrupt

CSR7, bit 0

CSR7, bit 1

MAPINT

MII Auto-Poll

Interrupt

CSR7, bit 6

CSR7, bit 7

MREINT

MII

Management

Frame Read

Error Interrupt

CSR7, bit 8

CSR7, bit 9

STINT

Software Timer

Interrupt

CSR7, bit 10

CSR7, bit 11

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