AM79C973VCW datasheet(50/304 Pages) AMD

50 / 304 page

Am79C973/Am79C975

P R E L I M INARY

Figure 15 shows a typical burst write access. The

Am79C973/Am79C975 controller arbitrates for the bus,

is granted access, and writes four 32-bit words

(DWords) to the system memory and then releases the

bus. In this example, the memory system extends the

data phase of the first access by one wait state. The fol-

lowing three data phases take one clock cycle each,

which is determined by the timing of TRDY. The exam-

ple assumes that EXTREQ (BCR18, bit 8) is set to 1,

therefore, REQ is not deasserted until the next to last

data phase is finished.

Target Initiated Termination

When the Am79C973/Am79C975 controller is a bus

master, the cycles it produces on the PCI bus may be

terminated by the target in one of three different ways:

disconnect with data transfer, disconnect without data

transfer, and target abort.

Disconnect With Data Transfer

Figure 16 shows a disconnection in which one last data

transfer occurs after the target asserted STOP. STOP

is asserted on clock 4 to start the termination se-

quence. Data is still transferred during this cycle, since

both IRDY and TRDY are asserted. The Am79C973/

Am79C975 controller terminates the current transfer

with the deassertion of FRAME on clock 5 and of IRDY

one clock later. It finally releases the bus on clock 7.

The Am79C973/Am79C975 controller will again re-

quest the bus after two clock cycles, if it wants to trans-

fer more data. The starting address of the new transfer

will be the address of the next non-transferred data.

Figure 15. Burst Write Transfer (EXTREQ = 1)

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

2345678

ADDR

DATA

0111

PAR

DATA

PAR

DEVSEL

is sampled

21510D-20

AM79C973VCW Datasheet(PDF) 50 Page - Advanced Micro Devices

AM79C973VCW Datasheet(HTML) 50 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL