AM79C973VCW datasheet(65/304 Pages) AMD

65 / 304 page

Am79C973/Am79C975

P R E L I M INARY

family. The descriptor ring base addresses must be

aligned to an 8-byte boundary and a maximum of 128

ring entries is allowed when the ring length is set

through the TLEN and RLEN fields of the initialization

block. Each ring entry contains a subset of the three

32-bit transmit or receive message descriptors (TMD,

RMD) that are organized as four 16-bit structures

(SSIZE32 (BCR20, bit 8) is set to 0). Note that even

though the Am79C973/Am79C975 controller treats the

descriptor entries as 16-bit structures, it will always

perform 32-bit bus transfers to access the descriptor

entries. The value of CSR2, bits 15-8, is used as the

upper 8-bits for all memory addresses during bus mas-

ter transfers.

When SWSTYLE is set to 2 or 3, the descriptor ring

base addresses must be aligned to a 16-byte bound-

ary, and a maximum of 512 ring entries is allowed when

the ring length is set through the TLEN and RLEN fields

of the initialization block. Each ring entry is organized

as three 32-bit message descriptors (SSIZE32

(BCR20, bit 8) is set to 1). The fourth DWord is re-

served. When SWSTYLE is set to 3, the order of the

message descriptors is optimized to allow read and

write access in burst mode.

For any software style, the ring lengths can be set be-

yond this range (up to 65535) by writing the transmit

and receive ring length registers (CSR76, CSR78) di-

rectly.

Each ring entry contains the following information:

s The address of the actual message data buffer in

user or host memory

s The length of the message buffer

s Status information indicating the condition of the

buffer

To permit the queuing and de-queuing of message

buffers, ownership of each buffer is allocated to either

the Am79C973/Am79C975 controller or the host. The

OWN bit within the descriptor status information, either

TMD or RMD, is used for this purpose.

When OWN is set to 1, it signifies that the Am79C973/

Am79C975 controller currently has ownership of this

ring descriptor and its associated buffer. Only the

owner is permitted to relinquish ownership or to write to

any field in the descriptor entry. A device that is not the

current owner of a descriptor entry cannot assume

ownership or change any field in the entry. A device

may, however, read from a descriptor that it does not

currently own. Software should always read descriptor

entries in sequential order. When software finds that

the current descriptor is owned by the Am79C973/

Am79C975 controller, then the software must not read

ahead to the next descriptor. The software should wait

at a descriptor it does not own until the Am79C973/

Am79C975 controller sets OWN to 0 to release owner-

ship to the software. (When LAPPEN (CSR3, bit 5) is

set to 1, this rule is modified. See the LAPPEN descrip-

tion. At initialization, the Am79C973/Am79C975 con-

troller reads the base address of both the transmit and

receive descriptor rings into CSRs for use by the

Am79C973/Am79C975 controller during subsequent

operations.

Figure 31 illustrates the relationship between the initial-

ization base address, the initialization block, the re-

ceive and transmit descriptor ring base addresses, the

receive and transmit descriptors, and the receive and

transmit data buffers, when SSIZE32 is cleared to 0.

AM79C973VCW Datasheet(PDF) 65 Page - Advanced Micro Devices

AM79C973VCW Datasheet(HTML) 65 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL