AM79C973VCW datasheet(78/304 Pages) AMD

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Am79C973/Am79C975

P R E L I M INARY

s FCS errors

s Late collision

Host related receive exception conditions include

MISS, BUFF, and OFLO. These are described in the

section, Buffer Management Unit.

Loopback Operation

Loopback is a mode of operation intended for system

diagnostics. In this mode, the transmitter and receiver

are both operating at the same time so that the control-

ler receives its own transmissions. The controller pro-

vides two basic types of loopback. In internal loopback

mode, the transmitted data is looped back to the re-

ceiver inside the controller without actually transmitting

any data to the external network. The receiver will

move the received data to the next receive buffer,

where it can be examined by software. Alternatively, in

external loopback mode, data can be transmitted to

and received from the external network.

Refer to Table 21 for various bit settings required for

Loopback modes.

The external loopback requires a two-step operation.

The internal PHY must be placed into a loopback mode

by writing to the PHY Control Register (BCR33,

BCR34). Then, the Am79C973/Am79C975 controller

must be placed into an external loopback mode by set-

ting the Loop bits.

Miscellaneous Loopback Features

All transmit and receive function programming, such as

automatic transmit padding and receive pad stripping,

operates identically in loopback as in normal operation.

Runt Packet Accept is internally enabled (RPA bit in

CSR124 is not affected) when any loopback mode is in-

voked. This is to be backwards compatible to the C-

LANCE (Am79C90) software.

Since the Am79C973/Am79C975 controller has two

FCS generators, there are no more restrictions on FCS

generation or checking, or on testing multicast address

detection as they exist in the half-duplex PCnet family

device s a nd in the C-LANCE. On receive, th e

Am79C973/Am79C975 controller now provides true

FCS status. The descriptor for a frame with an FCS

error will have the FCS bit (RMD1, bit 27) set to 1. The

FCS generator on the transmit side can still be disabled

by setting DXMTFCS (CSR15,

bit 3) to 1.

In internal loopback operation, the Am79C973/

Am79C975 controller provides a special mode to test

the collision logic. When FCOLL (CSR15, bit 4) is set

to 1, a collision is forced during every transmission at-

tempt. This will result in a Retry error.

Full-Duplex Operation

The Am79C973/Am79C975 controller supports full-du-

plex operation on both network interfaces. Full-duplex

operation allows simultaneous transmit and receive ac-

tivity. Full-duplex operation is enabled by the FDEN bit

located in BCR9. Full-duplex operation is also enabled

through Auto-Negotiation when DANAS (BCR 32, bit 7)

is not enabled and the ASEL bit is set, and its link partner

is capable of Auto-Negotiation and full-duplex opera-

tion.

When operating in full-duplex mode, the following

changes to the device operation are made:

Bus Interface/Buffer Management Unit changes:

s The first 64 bytes of every transmit frame are not

preserved in the Transmit FIFO during transmission

of the first 512 bits as described in the Transmit Ex-

ception Conditions section. Instead, when full-du-

plex mode is active and a frame is being transmitted,

the XMTFW bits (CSR80, bits 9-8) always govern

when transmit DMA is requested.

s Successful reception of the first 64 bytes of every

receive frame is not a requirement for Receive DMA

to begin as described in the Receive Exception Con-

ditions section. Instead, receive DMA will be re-

quested as soon as either the RCVFW threshold

(CSR80, bits 12-13) is reached or a complete valid

receive frame is detected, regardless of length. This

Receive FIFO operation is identical to when the RPA

bit (CSR124, bit 3) is set during half-duplex mode

operation.

The MAC engine changes for full-duplex operation are

as follows:

s Changes to the Transmit Deferral mechanism:

— Transmission is not deferred while receive is

active.

— The IPG counter which governs transmit deferral

during the IPG between back-to-back transmits

is started when transmit activity for the first

packet ends, instead of when transmit and car-

rier activity ends.

s The 4.0 µs carrier sense blinding period after a

transmission during which the SQE test normally

occurs is disabled.

s The collision indication input to the MAC engine is

ignored.

The internal PHY changes for full-duplex operation are

as follows:

s The collision detect (COL) pin is disabled.

s The SQE test function is disabled (10 Mbps).

s Loss of Carrier (LCAR) reporting is disabled.

AM79C973VCW Datasheet(PDF) 78 Page - Advanced Micro Devices

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