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AM79C973VCW Datasheet(PDF) 81 Page - Advanced Micro Devices |
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AM79C973VCW Datasheet(HTML) 81 Page - Advanced Micro Devices |
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81 / 304 page ![]() Am79C973/Am79C975 81 P R E L I M INARY Figure 35. 100BASE-X Transmit and Receive Data Paths of the Internal PHY Serial O/P Symbol O/P Loopback Paths 4B/5B Encoder /J/K/ Insertion /T/R/ Insertion 1 0 5 DISALIGN PDX 5 5 1 0 Scrambler Serializer TX_EN DISSCR 5 5 5 Deserializer Clock Recovery RSCLK PDX SDI ± 1 0 1 0 5B/4B Decoder Code Align Descrambler DISALIGN LBK[1:0]=10 LBK[1:0]=11 DISSCR 10 5 5 5 5 5 5 1 0 RXD[3:0] & RX_ER RX_DV TXD[3:0] & TX_ER PECL Conversion MLT-3 Conversion with Adaptive Equalization and Baseline Restoration RX ± PECL Conversion MLT-3 Conversion TX ± SDI ± SDI ± Note: The 5-bit mode bypasses Encoder/Decoder and Scrambler/Descrambler logic. Internal MII-Compatible Interface Internal MII-Compatible Interface 21510D-40 |
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