AM79C973VCW datasheet(89/304 Pages) AMD

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Am79C973/Am79C975

P R E L I M INARY

ler, unless the EAR pin becomes active during the first

64 bytes of the frame (excluding preamble and SFD).

This allows external address lookup logic approxi-

mately 58 byte times after the last destination address

bit is available to generate the EAR signal, assuming

that the Am79C973/Am79C975 controller is not config-

ured to accept runt packets. The EADI logic only sam-

ples EAR from 2 bit times after SFD until 512 bit times

(64 bytes) after SFD. The frame will be accepted if EAR

has not been asserted during this window. In order for

the EAR pin to be functional in full-duplex mode, FDR-

PAD bit (BCR9, bit 2) needs to be set. If Runt Packet

Accept (CSR124, bit 3) is enabled, then the EAR signal

must be generated prior to the 8 bytes received, if

frame rejection is to be guaranteed. Runt packet sizes

could be as short as 12 byte times (assuming 6 bytes

for source address, 2 bytes for length, no data, 4 bytes

for FCS) after the last bit of the destination address is

available. EAR must have a pulse width of at least 110

ns.

The EADI outputs continue to provide data throughout

the reception of a frame. This allows the external logic

to capture frame header information to determine pro-

tocol type, internetworking information, and other use-

ful data.

The EADI interface will operate as long as the STRT bit

in CSR0 is set, even if the receiver and/or transmitter

are disabled by software (DTX and DRX bits in CSR15

are set). This configuration is useful as a semi-power-

down mode in that the Am79C973/Am79C975 control-

ler will not perform any power-consuming DMA opera-

tions. However, external circuitry can still respond to

control frames on the network to facilitate remote node

control. Table 11 summarizes the operation of the EADI

interface.

External Address Detection Interface: MII Snoop

Mode

The MII Snoop mode provides all necessary data and

clock signals needed for the EADI interface. Data for

the EADI is the RXD[3:0] receive data provided to the

internal MII. The user will receive the data as 4 bit nib-

bles. RX_CLK is provided to allow clocking of the

RXD[3:0] receive nibble stream into the external ad-

dress detection logic. The RXD[3:0] data is synchro-

nous to the rising edge of the RX_CLK. The data

arrives in nibbles and can be at a rate of 25 MHz or 2.5

MHz.

The assertion of SFBD is a signal to the external ad-

dress detection logic that the SFD has been detected

and that the first valid data nibble is on the RXD[3:0]

data bus. The SFBD signal is delayed one RX_CLK

cycle from the above definition and actually signals the

start of valid data. In order to reduce the amount of

logic external to the Am79C973/Am79C975 controller

for multiple address decoding systems, the SFBD sig-

nal will go HIGH at each new byte boundary within the

packet, subsequent to the SFD. This eliminates the

need for externally supplying byte framing logic.

The EAR pin should be driven LOW by the external ad-

dress comparison logic to reject a frame.

External Address Detection Interface: Receive

Frame Tagging

The Am79C973/Am79C975 controller supports re-

ceive frame tagging in MII Snoop mode. The receive

frame tagging implementation is a two-wire chip inter-

face in addition to the existing EADI.

The Am79C973/Am79C975 controller supports up to

15 bits of receive frame tagging per frame in the receive

frame status (RFRTAG). The RFRTAG bits are in the

receive frame status field in RMD2 (bits 30-16) in 32-bit

software mode. The receive frame tagging is not sup-

ported in the 16-bit software mode. The RFRTAG field

are all zeros when either the EADISEL (BCR2, bit3) or

the RXFRTAG (CSR7, bit 14) are set to 0. When

EADISEL (BCR2, bit 3) and RXFRTAG (CSR7, bit 14)

are set to 1, then the RFRTAG reflects the tag word

shifted in during that receive frame.

In the MII Snoop mode, the two-wire interface will use

the MIIRXFRTGD and MIIRXFRTGE pins from the

EADI interface. These pins will provide the data input

and data input enable for the receive frame tagging, re-

spectively. These pins are normally not used during the

MII operation.

The receive frame tag register is a shift register that

shifts data in MSB first, so that less than the 15 bits al-

located may be utilized by the user. The upper bits not

utilized will return zeros. The receive frame tag register

is set to 0 in between reception of frames. After receiv-

ing SFBD indication on the EADI, the user can start

shifting data into the receive tag register until one net-

work clock period before the Am79C973/Am79C975

controller receives the end of the current receive frame.

In the MII Snoop mode, the user must see the RX_CLK

to drive the synchronous receive frame tag data inter-

face. After receiving the SFBD indication, sampled by

the rising edge of the RX_CLK, the user will drive the

data input and the data input enable synchronous with

the rising edge of the RX_CLK. The user has until one

network clock period before the deassertion of the

Table 11. EADI Operations

PROM

EAR

Required

Timing

Received

Frames

No timing

requirements

All received frames

No timing

requirements

All received frames

Low for two bit

times plus 10 ns

Frame rejected if in

address match

mode

AM79C973VCW Datasheet(PDF) 89 Page - Advanced Micro Devices

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