AM79C973VCW datasheet(41/304 Pages) AMD

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Am79C973/Am79C975

P R E L I M INARY

Am79C973/Am79C975 controllers assert DEVSEL if it

detects an address match and the access is a memory

cycle. DEVSEL is asserted two clock cycles after the

host has asserted FRAME. See Figure 1 and Figure 2.

Figure 1. Slave Configuration Read

The Am79C973/Am79C975 controllers will not assert

DEVSEL if it detects an address match and the PCI

command is not of the correct type. In memory mapped

I/O mode, the Am79C973/Am79C975 controller aliases

all accesses to the I/O resources of the command types

Memory Read Multiple and Memory Read Line to the

basic Memory Read command. All accesses of the type

Memory Write and Invalidate are aliased to the basic

Memory Write command. Eight-bit, 16-bit, and 32-bit

non-burst transactions are supported. The Am79C973/

Am79C975 controllers decode all 32 address lines to

determine which I/O resource is accessed.

The typical number of wait states added to a slave I/O

or memory mapped I/O read or write access on the part

of the Am79C973/Am79C975 controllers are six to sev-

en clock cycles, depending upon the relative phases of

the internal Buffer Management Unit clock and the CLK

signal, since the internal Buffer Management Unit clock

is a divide-by-two version of the CLK signal.

The Am79C973/Am79C975 controllers do not support

burst transfers for access to its I/O resources. When the

host keeps FRAME asserted for a second data phase,

the Am79C973/Am79C975 controllers will disconnect

the transfer.

Figure 2. Slave Configuration Write

The Am79C973/Am79C975 controllers support fast

back-to-back transactions to different targets. This is

indicated by the Fast Back-To-Back Capable bit (PCI

Status register, bit 7), which is hardwired to 1. The

Am79C973/Am79C975 controllers are capable of de-

tecting an I/O or a memory-mapped I/O cycle even when

its address phase immediately follows the data phase

of a transaction to a different target, without any idle

state in-between. There will be no contention on the

DEVSEL,

TRDY,

and STOP

signals, since the

Am79C973/Am79C975 controllers assert DEVSEL on

the second clock after FRAME is asserted (medium tim-

ing) See Figure 3 and Figure 4.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

IDSEL

23456

1010

PAR

DEVSEL

is sampled

DATA

ADDR

21510D-6

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

IDSEL

23456

1011

PAR

DATA

ADDR

21510D-7

AM79C973VCW Datasheet(PDF) 41 Page - Advanced Micro Devices

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