AM79C973VCW datasheet(63/304 Pages) AMD

63 / 304 page

Am79C973/Am79C975

P R E L I M INARY

Figure 30. FIFO Burst Write At End Of Unaligned

Buffer

The exact number of total transfer cycles in the bus

mastership period is dependent on all of the following

variables: the settings of the FIFO watermarks, the

conditions of the FIFOs, the latency of the system bus

to the Am79C973/Am79C975 controller’s bus request,

and the speed of bus operation. The TRDY response

time of the memory device will also affect the number

of transfers, since the speed of the accesses will affect

the state of the FIFO. During accesses, the FIFO may

be filling or emptying on the network end. For example,

on a receive operation, a slower TRDY response will

allow additional data to accumulate inside of the FIFO.

If the accesses are slow enough, a complete DWord

may become available before the end of the bus mas-

tership period and, thereby, increase the number of

transfers in that period. The general rule is that the

longer the Bus Grant latency, the slower the bus trans-

fer operations; the slower the clock speed, the higher

the transmit watermark; or the lower the receive water-

mark, the longer the total burst length will be.

When a FIFO DMA burst operation is preempted, the

Am79C973/Am79C975 controller will not relinquish

bus ownership until the PCI Latency Timer expires.

Buffer Management Unit

The Buffer Management Unit (BMU) is a microcoded

state machine which implements the initialization pro-

cedure and manages the descriptors and buffers. The

buffer management unit operates at half the speed of

the CLK input.

Initialization

Am79C973/Am79C975 initialization includes the read-

ing of the initialization block in memory to obtain the op-

erating parameters. The initialization block can be

organized in two ways. When SSIZE32 (BCR20, bit 8)

is at its default value of 0, all initialization block entries

are logically 16-bits wide to be backwards compatible

with the Am79C90 C-LANCE and Am79C96x PCnet-

ISA family. When SSIZE32 (BCR20, bit 8) is set to 1, all

initialization block entries are logically 32-bits wide.

Note that the Am79C973/Am79C975 controller always

performs 32-bit bus transfers to read the initialization

block entries. The initialization block is read when the

INIT bit in CSR0 is set. The INIT bit should be set be-

fore or concurrent with the STRT bit to insure correct

operation. Once the initialization block has been com-

pletely read in and internal registers have been up-

dated, IDON will be set in CSR0, generating an

interrupt (if IENA is set).

The Am79C973/Am79C975 controller obtains the start

address of the initialization block from the contents of

CSR1 (least significant 16 bits of address) and CSR2

(most significant 16 bits of address). The host must

write CSR1 and CSR2 before setting the INIT bit. The

initialization block contains the user defined conditions

for Am79C973/Am79C975 operation, together with the

base addresses and length information of the transmit

and receive descriptor rings.

There is an alter nate method to initial ize the

Am79C973/Am79C975 controller. Instead of initializa-

tion via the initialization block in memory, data can be

written directly into the appropriate registers. Either

method or a combination of the two may be used at the

discretion of the programmer. Please refer to Appendix

A, Alternative Method for Initialization for details on this

alternate method.

Re-Initialization

T he transmit t er and r e ceiver sect ions of the

Am79C973/Am79C975 controller can be turned on via

the initialization block (DTX, DRX, CSR15, bits 1-0).

The states of the transmitter and receiver are moni-

tored by the host through CSR0 (RXON, TXON bits).

The Am79C973/Am79C975 controller should be re-ini-

tialized if the transmitter and/or the receiver were not

turned on during the original initialization, and it was

subsequently required to activate them or if either sec-

tion was shut off due to the detection of an error condi-

tion (MERR, UFLO, TX BUFF error).

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

234567

0000

0111

PAR

DEVSEL

is sampled

1110

PAR

DATA

ADD

21510D-35

AM79C973VCW Datasheet(PDF) 63 Page - Advanced Micro Devices

AM79C973VCW Datasheet(HTML) 63 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL