AM79C973VCW datasheet(47/304 Pages) AMD

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Am79C973/Am79C975

P R E L I M INARY

starts driving AD[31:0] and C/BE[3:0] on clock 5.

FRAME is asserted at clock 5 indicating a valid ad-

dress and command on AD[31:0] and C/BE[3:0].

Figure 11. Bus Acquisition

In burst mode, the deassertion of REQ depends on the

setting of EXTREQ (BCR18, bit 8). If EXTREQ is

cleared to 0, REQ is deasserted at the same time as

FRAME is asserted. (The Am79C973/Am79C975 con-

troller never performs more than one burst transaction

within a single bus mastership period.) If EXTREQ is

set to 1, the Am79C973/Am79C975 controller does not

deassert REQ until it starts the last data phase of the

transaction. Once asserted, REQ remains active until

GNT has become active and independent of subse-

quent setting of STOP (CSR0, bit 2) or SPND (CSR5,

bit 0). The assertion of H_RESET or S_RESET, how-

ever, will cause REQ to go inactive immediately.

Bus Master DMA Transfers

There are four primary types of DMA transfers. The

Am79C973/Am79C975 controller uses non-burst as

well as burst cycles for read and write access to the

main memory.

Basic Non-Burst Read Transfer

By default, the Am79C973/Am79C975 controller uses

non-burst cycles in all bus master read operations. All

Am79C973/Am79C975 controller non-burst read ac-

cesses are of the PCI

command type Memory Read

(type 6). Note that during a non-burst read operation,

all byte lanes will always be active. The Am79C973/

Am79C975 controller will internally discard unneeded

bytes.

The Am79C973/Am79C975 controller typically per-

forms more than one non-burst read transaction within

a single bus mastership period. FRAME is dropped be-

tween consecutive non-burst read cycles. REQ how-

ever stays asserted until FRAME is asserted for the last

transaction. The Am79C973/Am79C975 controller

supports zero wait state read cycles. It asserts IRDY

immediately after the address phase and at the same

time starts sampling DEVSEL. Figure 12 shows two

non-burst read transactions. The first transaction has

zero wait states. In the second transaction, the target

extends the cycle by asserting TRDY one clock later.

Basic Burst Read Transfer

The Am79C973/Am79C975 controller supports burst

mode for all bus master read operations. The burst

mode must be enabled by setting BREADE (BCR18, bit

6). To allow burst transfers in descriptor read opera-

tions, the Am79C973/Am79C975 controller must also

be programmed to use SWSTYLE 3 (BCR20, bits 7-0).

All burst read accesses to the initialization block and

descriptor ring are of the PCI command type Memory

Read (type 6). Burst read accesses to the transmit

buffer typically are longer than two data phases. When

MEMCMD (BCR18, bit 9) is cleared to 0, all burst read

accesses to the transmit buffer are of the PCI com-

mand type Memory Read Line (type 14). When MEM-

CMD (BCR18, bit 9) is set to1, all burst read accesses

to the transmit buffer are of the PCI command type

Memory Read Multiple (type 12). AD[1:0] will both be 0

during the address phase indicating a linear burst or-

der. Note that during a burst read operation, all byte

lan e s w ill always be act i ve . The Am7 9 C 9 73/

Am79C975 controller will internally discard unneeded

bytes.

The Am79C973/Am79C975 controller will always per-

form only a single burst read transaction per bus mas-

tership period, where transaction is defined as one

address phase and one or multiple data phases. The

Am79C973/Am79C975 controller supports zero wait

state read cycles. It asserts IRDY immediately after the

address phase and at the same time starts sampling

DEVSEL. FRAME is deasserted when the next to last

data phase is completed.

Figure 13 shows a typical burst read access. The

Am79C973/Am79C975 controller arbitrates for the bus,

is granted access, reads three 32-bit words (DWord)

from the system memory, and then releases the bus. In

the example, the memory system extends the data

phase of each access by one wait state. The example

assumes that EXTREQ (BCR18, bit 8) is cleared to 0,

therefore, REQ is deasserted in the same cycle as

FRAME is asserted.

FRAME

CLK

IRDY

C/BE

REQ

GNT

2345

CMD

ADDR

21510D-16

AM79C973VCW Datasheet(PDF) 47 Page - Advanced Micro Devices

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