AM79C973VCW datasheet(34/304 Pages) AMD

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Am79C973/Am79C975

P R E L I M INARY

EBDA[15:8]

Expansion Bus Data/Address [15:8]

Input/

Output

When EROMCS is asserted low, EBDA[15:8] contain

address bits [15:8] for boot device accesses.

The EBDA[15:8] signals are driven to a constant level

to conserve power while no access on the Expansion

Bus is being performed.

Note: EBDA[15:8] pins are multiplexed with the

TXD[3:0], TX_EN, MDIO, CRS, and COL pins.

EBD[7:0]

Expansion Bus Data [7:0]

Input/Output

The EBD[7:0] pins provide data bits [7:0] for EPROM/

FLASH accesses. The EBD[7:0] signals are internally

forced to a constant level to conserve power while no

access on the Expansion Bus is being performed.

Note: EBD[7:0]

pins

are

multiplexed

with

the

RXD[3:0], RX_DV, RX_CLK, RX_ER, and TX_CLK

pins.

EROMCS

Expansion ROM Chip Select

Output

EROMCS serves as the chip select for the boot device.

It is asserted low during the data phases of boot device

accesses.

AS_EBOE

Address Strobe/Expansion Bus

Output Enable

Output

AS_EBOE functions as the address strobe for the

upper address bits on the EBUA_EBA[7:0] pins and as

the output enable for the Expansion Bus.

As an address strobe, a rising edge on AS_EBOE is

supplied at the beginning of boot device accesses. This

rising edge provides a clock edge for a ‘374 D-type

edge-triggered flip-flop which must store the upper ad-

dress byte during Expansion Bus accesses for

EPROM/Flash.

AS_EBOE is asserted active LOW during boot device

read operations on the expansion bus and is deas-

serted during boot device write operations.

EBWE

Expansion Bus Write Enable

Output

EBWE provides the write enable for write accesses to

the Flash device.

EBCLK

Expansion Bus Clock

Input

EBCLK may be used as the fundamental clock to drive

the Expansion Bus and internal SRAM access cycles.

The actual internal clock used to drive the Expansion

Bus cycles depends on the values of the EBCS and

CLK_FAC settings in BCR27. Refer to the SRAM Inter-

face Bandwidth Requirements section for details on de-

termining the required EBCLK frequency. If a clock

source other than the EBCLK pin is programmed

(BCR27, bits 5:3) to be used to run the Expansion Bus

interface, this input should be tied to VDD through a 4.7

kW resistor.

EBCLK is not used to drive the bus interface, internal

buffer management unit, or the network functions.

Media Independent Interface (MII)

TX_CLK

Transmit Clock

Input

TX_CLK is a continuous clock input that provides the

timing reference for the transfer of the TX_EN,

TXD[3:0], and TX_ER signals out of the Am79C973/

Am79C975 device. TX_CLK must provide a nibble rate

clock (25% of the network data rate). Hence, an MII

transceiver operating at 10 Mbps must provide a

TX_CLK frequency of 2.5 MHz and an MII transceiver

operating at 100 Mbps must provide a TX_CLK fre-

quency of 25 MHz.

Note: The TX_CLK pin is multiplexed with the EBD7

pin.

TXD[3:0]

Transmit Data

Output

TXD[3:0] is the nibble-wide MII transmit data bus. Valid

data is generated on TXD[3:0] on every TX_CLK rising

edge while TX_EN is asserted. While TX_EN is de-

asserted, TXD[3:0] values are driven to a 0. TXD[3:0]

transitions synchronous to TX_CLK rising edges.

Note: The TXD[3:0] pins are multiplexed with the

EBDA[11:8] pins.

TX_EN

Transmit Enable

Output

TX_EN indicates when the Am79C973/Am79C975 de-

vice is presenting valid transmit nibbles on the MII.

While TX_EN is asserted, the Am79C973/Am79C975

device generates TXD[3:0] and TX_ER on TX_CLK ris-

ing edges. TX_EN is asserted with the first nibble of

preamble and remains asserted throughout the dura-

tion of a packet until it is deasserted prior to the first

TX_CLK following the final nibble of the frame. TX_EN

transitions synchronous to TX_CLK rising edges.

Note: The TX_EN pin is multiplexed with the EBDA12

pin.

TX_ER

Transmit Error

Output

TX_ER is an output that, if asserted while TX_EN is as-

serted, instructs the MII PHY device connected to the

Am79C973/Am79C975 device to transmit a code

AM79C973VCW Datasheet(PDF) 34 Page - Advanced Micro Devices

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