DS2152 datasheet(64/94 Pages) DALLAS

64 / 94 page

DS2152

64 of 93

11.2 LEGACY FDL SUPPORT

11.2.1 Overview

In order to provide backward compatibility to the older DS2151 device, the DS2152 maintains the

circuitry that existed in the previous generation of T1 Single-Chip Transceivers. Section 11.2 covers the

circuitry and operation of this legacy functionality. In new applications, it is recommended that the

HDLC controller and BOC controller described in Section 11.1 be used. On the receive side, it is possible

to have both the new HDLC/BOC controller and the legacy hardware working at the same time.

However, this is not possible on the transmit side since their can be only one source the of the FDL data

internal to the device.

11.2.2 Receive Section

In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the Receive FDL

DS2152 will signal an external microcontroller that the buffer has filled via the SR2.4 bit. If enabled via

IMR2.4, the INT pin will toggle low indicating that the buffer has filled and needs to be read. The user

has 2 ms to read this data before it is lost.

If the byte in the RFDL matches either of the bytes

programmed into the RFDLM1 or RFDLM2 registers, then the SR2.2 bit will be set to a 1 and the INT

pin will toggled low if enabled via IMR2.2. This feature allows an external microcontroller to ignore the

FDL or Fs pattern until an important event occurs.

The DS2152 also contains a 0 destuffer which is controlled via the CCR2.0 bit. In both ANSI T1.403 and

TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states

that no more than five 1s should be transmitted in a row so that the data does not resemble an opening or

closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.0, the DS2152 will

automatically look for five 1s in a row, followed by a 0. If it finds such a pattern, it will automatically

remove the 0. If the 0 destuffer sees six or more 1s in a row followed by a 0, the 0 is not removed. The

CCR2.0 bit should always be set to a 1 when the DS2152 is extracting the FDL. More on how to use the

DS2152 in FDL applications in this legacy support mode is covered in a separate Application Note.

RFDL: RECEIVE FDL REGISTER (Address=28 Hex)

(MSB)

(LSB)

RFDL7

RFDL6

RFDL5

RFDL4

RFDL3

RFDL2

RFDL1

RFDL0

SYMBOL

POSITION

NAME AND DESCRIPTION

RFDL7

RFDL.7

MSB of the Received FDL Code

RFDL0

RFDL.0

LSB of the Received FDL Code

The Receive FDL Register (RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fs

bits. The LSB is received first.

DS2152 Datasheet(PDF) 64 Page - Dallas Semiconductor

DS2152 Datasheet(HTML) 64 Page - Dallas Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

Datasheet Download

Link URL