DS2152 datasheet(23/94 Pages) DALLAS

23 / 94 page

DS2152

23 of 93

Payload Loopback

When CCR1.1 is set to a 1, the DS2152 will be forced into Payload LoopBack (PLB). Normally, this

loopback is only enabled when ESF framing is being performed but can be enabled also in D4 framing

applications. In a PLB situation, the DS2152 will loop the 192 bits of payload data (with BPVs corrected)

from the receive section back to the transmit section. The FPS framing pattern, CRC6 calculation, and the

FDL bits are not looped back, they are reinserted by the DS2152. When PLB is enabled, the following

will occur:

1. data will be transmitted from the TPOSO and TNEGO pins synchronous with RCLK instead of

TCLK

2. all of the receive side signals will continue to operate normally

3. the TCHCLK and TCHBLK signals are forced low

4. data at the TSER, TDATA, and TSIG pins is ignored

5. the TLCLK signal will become synchronous with RCLK instead of TCLK.

Framer Loopback

When CCR1.0 is set to a 1, the DS2152 will enter a Framer LoopBack (FLB) mode. This loopback is

useful in testing and debugging applications. In FLB, the DS2152 will loop data from the transmit side

back to the receive side. When FLB is enabled, the following will occur:

1. an unframed all 1s code will be transmitted at TPOSO and TNEGO

2. data at RPOSI and RNEGI will be ignored

3. all receive side signals will take on timing synchronous with TCLK instead of RCLKI.

Please note that it is not acceptable to have RCLK tied to TCLK during this loopback because this will

cause an unstable condition.

DS2152 Datasheet(PDF) 23 Page - Dallas Semiconductor