DS2152 datasheet(17/94 Pages) DALLAS

17 / 94 page

DS2152

17 of 93

NOTES:

1. Test Registers 1 and 2 are used only by the factory; these registers must be cleared (set to all 0s) on

power-up initialization to insure proper operation.

2. Register banks 9xh, Axh, Bxh, Cxh, Dxh, Exh, and Fxh are not accessible.

2.0 PARALLEL PORT

The DS2152 is controlled via either a non-multiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by an

external microcontroller or microprocessor. The DS2152 can operate with either Intel or Motorola bus

timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola

timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in

the A.C. Electrical Characteristics in Section 16 for more details.

3.0 CONTROL, ID AND TEST REGISTERS

The operation of the DS2152 is configured via a set of eleven control registers. Typically, the control

registers are only accessed when the system is first powered up. Once the DS2152 has been initialized,

the control registers will only need to be accessed when there is a change in the system configuration.

There are two Receive Control Register (RCR1 and RCR2), two Transmit Control Registers (TCR1 and

TCR2), and seven Common Control Registers (CCR1 to CCR7).

Each of the eleven registers are

described in this section.

There is a device IDentification Register (IDR) at address 0Fh. The MSB of this read-only register is

fixed to a 0 indicating that the DS2152 is present. The E1 pin-for-pin compatible version of the DS2152

is the DS2154, which also has an ID register at address 0Fh. The user can read the MSB to determine

which chip is present since in the DS2152 the MSB will be set to a 0 and in the DS2154 it will be set to a

1. The lower 4 bits of the IDR are used to display the die revision of the chip.

IDR: DEVICE IDENTIFICATION REGISTER (Address=0F Hex)

(MSB)

(LSB)

T1E1

ID3

ID2

ID1

ID0

SYMBOL

POSITION

NAME AND DESCRIPTION

T1E1

IDR.7

T1 or E1 Chip Determination Bit.

0=T1 chip

1=E1 chip

ID3

IDR.3

Chip Revision Bit 3. MSB of a decimal code that represents the

chip revision.

ID2

IDR.1

Chip Revision Bit 2.

ID1

IDR.2

Chip Revision Bit 1.

ID0

IDR.0

Chip Revision Bit 0. LSB of a decimal code that represents the

chip revision.

The two Test Registers at addresses 09 and 7D hex are used by the factory in testing the DS2152. On

power-up, the Test Registers should be set to 00 hex in order for the DS2152 to operate properly.

DS2152 Datasheet(PDF) 17 Page - Dallas Semiconductor

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