ASI4U datasheet(29/64 Pages) ETC2

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ASI4U / ASI4U-E / ASI4U-F

Spec. 3.0 Compliant Universal AS-I IC

Data Sheet

April 2, 2012

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4. The UART is constantly set to Synchronous Receive Mode. This is because the signal sequence that

is generated by the handheld programming device exhibits an additional signal transition in a time

frame of 3 bit times after the end of the transmitted master call.

3.3.2.

AC Current Input Mode

The IRD input allows direct connection of a Photo-Diode (referencing to 0V) and senses the generated photo

current. A valid input signal has to have certain current amplitude (range) and must not exceed a certain offset

current value (Table 10 and Figure 8).

In contrast to A²SI versions, the IRD input of the ASI4U covers the entire input current range by a single

amplifying stage with continues (logarithmical) gain adaptation. Thus, the cyclical gain switching is avoided

and the IC can react more safely and without delay on different input signal amplitudes.

Table 10: IRD AC current input parameters

Symbol Parameter

Min

Max

Unit

Note

IIRDO

Input current offset

µA

IIRDA

Input current amplitude

100

µA

MIN

IIRDA

MAX

IIRDA

MAX

IIRDO

time

IRD

input

current

Figure 8: Addressing Channel Input (IRD), Photo-current Waveforms

Following photo-diode is suggested for optimal performance:

 TEMIC TEMD5000

3.3.3.

CMOS Input Mode

In addition to the AC current input mode, the IRD input can also operate in CMOS input mode. Mode switching

is only possible as long as the IC has not locked to the Addressing Channel by reception of a Magic Sequence

already. On principle, that input mode that lead to the activation of the Addressing Channel will remain locked

until the Addressing Channel is deactivated (by IC Reset).

The CMOS mode is entered if the IRD input voltage is above 2.5V (logic high) for more than 7.680 ms (-

6.66%). It is left, if the IRD input voltage is below 1.0V (logic low) for more than 7.680 ms (-6.66%). The initial

input mode after IC initialization is determined at the end of the initialization phase and depends on the value

of the IRD input signal at that time.

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