ASI4U datasheet(32/64 Pages) ETC2

32 / 64 page

ASI4U / ASI4U-E / ASI4U-F

Spec. 3.0 Compliant Universal AS-I IC

Data Sheet

April 2, 2012

the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.

32 of 63

3.6. Parameter Port and PST Pin

3.6.1.

Slave Mode

The parameter port is configured for continuous bi-directional operation. Every pin contains an NMOS open

drain output driver plus a high voltage high impedance digital input stage. Received parameter output data is

stored at the Parameter Output Register and subsequently forwarded to the open drain output drivers. A

certain time (tPI-latch) after new output data has arrived at the port, the corresponding inputs are sampled.

The input value either results from a wired AND combination of the parameter output value and the signals

driven to the port by external sources (Multiplex_Parameter =’0’) or simply represents the externally driven

input signals (Multiplex_Parameter =’1’). For further explanation see also Figure 9 and chapter 3.6.2.

The availability of new parameter output data is signaled by the Parameter Strobe (PST) signal.

Besides the basic I/O function, the first parameter output event after an IC reset has an additional meaning. It

enables the data output at the Data Port (see chapters 3.7 and 3.11).

Any IC reset or the reception of a Delete_Address call turns the Parameter Output Register to 0xF and forces

the parameter output drivers to high impedance state. Simultaneously a Parameter Strobe is generated,

having the same tsetup timing and tPST pulse width, as new output data would be driven.

Table 16: Timing Parameter Port

Symbol Parameter

Min

Max

Unit

Note

tsetupL

Output data is valid LOW before PST-H/L

0.1

0.6

µs

tsetupH

Output driver is at high impedance state before PST-H/L

0.1

0.6

µs

thold

Output driver is at high impedance state after PST-H/L

0.1

0.6

µs

1, 2

tPST

Pulse width of Parameter Strobe (PST)

µs

tPI-latch

Acceptance of input data

13.5

µs

1 The designed value is 0.5µs.

2 thold is only valid, if the Multiplex_Parameter flag is set in the Firmware Area of the E²PROM.

3 The timing of the resulting voltage signal also depends on the external pull up resistor.

4 The parameter input data must be stable within the period defined by min. and max. values of t

PI-latch.

PST

tsetup

tPST

tPI-latch

parameter port output data

keep stable

min

max

P0..P3

PI0..PI3

parameter port input data

thold

data remains constant,

if Multiplex_Parameter

flag is not set

Hi-Z, if Multiplex_Parameter

flag is set

Figure 9: Timing Diagram Parameter Port P0 ... P3, PST

ASI4U Datasheet(PDF) 32 Page - List of Unclassifed Manufacturers

ASI4U Datasheet(HTML) 32 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Datasheet Download

Link URL