ASI4U datasheet(49/64 Pages) ETC2

49 / 64 page

ASI4U / ASI4U-E / ASI4U-F

Spec. 3.0 Compliant Universal AS-I IC

Data Sheet

April 2, 2012

the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.

49 of 63

Note: The power-on reset circuit has a threshold voltage reference. This reference matches the process

tolerance of the logic levels and must not be very accurate. All values depend slightly on the raise and

fall time of the supply voltage.

3.11.2. Logic controlled Reset

The IC also becomes reset after reception of Reset_Slave or Broadcast_Reset commands, expiration of the

(enabled) Communication Watchdog or entering of a forbidden state machine state (i.e. due to heavy EMI).

Note: In case the Addressing Channel is activated and the AC Current Input Mode is selected, Reset_Slave

and Broadcast_Reset calls are processed differently than in normal operation! See corresponding

explanations in chapter 3.3 Addressing Channel Input IRD on page 6.

3.11.3. External Reset

The IC can be reset externally by pulling the DSR pin LOW for more than a minimum reset time. The external

reset input function is provided in every operational mode of the IC – Slave Mode, Master Mode, Repeater

Mode and Monitor Mode. The following signal timings apply:

Table 32: Timing of external reset

Symbol Parameter

Min

Max

Unit

Note

tnoRESET DSR LOW time for no reset initiation

µs

tRESET

Reset execution time,

DSR H/L transition to Hi-Z output drives at DO0...DO3, P0…P3

µs

tINIT

State Machine initialization time after reset (E²PROM read out)

In contrast to the A²SI, the external reset is generated “edge sensitive” to the expiration of the tRESET timer. The

initialization procedure is starting immediately after the event, independent of the state of DSR. A Serious

Peripheral Fault is recognized in Slave Mode if DSR still remains LOW after tRESET + tINIT. The corresponding

error state display is described in chapter 3.9 LED outputs on page 6.

DSR

DO0..DO3

tnoRESET

tRESET

tINIT

Hi-Z

PO0..PO3

Hi-Z

data port output data

parameter port output data

Serious

Peripheral Fault

Figure 18: Timing diagram external Reset via DSR

ASI4U Datasheet(PDF) 49 Page - List of Unclassifed Manufacturers

ASI4U Datasheet(HTML) 49 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Datasheet Download

Link URL