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ADF7021

Data Sheet

Rev. B | Page 34 of 64

example, using 2FSK with Manchester-encoded data achieves a

data rate tolerance of ±2.0%.

The CDR PLL is designed for fast acquisition of the recovered

symbols during preamble and typically achieves bit synchro-

nization within 5-symbol transitions of preamble.

In 4FSK modulation, the tolerance using the +3, −3, +3, −3

preamble is ±3% of the symbol rate (or ±1.5% of the data rate).

However, this tolerance is reduced during recovery of the

remainder of the packet where symbol transitions may not be

guaranteed to occur at regular intervals. To maximize the

symbol/data rate tolerance, the remainder of the 4FSK packet

should be constructed so that the transmitted symbols retain close

to dc-free properties by using data scrambling and/or by inserting

specific dc balancing symbols that are inserted in the transmitted

bit stream at regular intervals such as after every 8 or 16 symbols.

In 3FSK modulation, the linear convolutional encoder scheme

guarantees that the transmitted symbol sequence is dc-free,

facilitating symbol detection. However, Tx data scrambling is

recommended to limit the run length of zero symbols in the

transmit bit stream. Using 3FSK, the CDR data rate tolerance is

typically ±0.5%.

RECEIVER SETUP

Correlator Demodulator Setup

To enable the correlator for various modulation modes, refer to

Table 16.

Table 16. Enabling the Correlator Demodulator

Received Modulation

DEMOD_SCHEME (R4_DB[4:6])

2FSK

001

3FSK

010

4FSK

011

To optimize receiver sensitivity, the correlator bandwidth must be

optimized for the specific deviation frequency and modulation

used by the transmitter. The discriminator bandwidth is

controlled by R4_DB[10:19] and is defined as

(

)

400

CLK

DEMOD

TOR

DISCRIMINA

where:

DEMOD CLK is as defined in the Register 3—Transmit/Receive

Clock Register section.

K is set for each modulation mode according to the following:

For 2FSK,













DEV

Round

100

For 3FSK,













DEV

Round

100

For 4FSK,













DEV

FSK

Round

100

where:

Round is rounded to the nearest integer.

Round4FSK is rounded to the nearest of the following integers: 32,

31, 28, 27, 24, 23, 20, 19, 16, 15, 12, 11, 8, 7, 4, 3.

fDEV is the transmit frequency deviation in Hz. For 4FSK, fDEV is

the frequency deviation used for the ±1 symbols (that is, the

inner frequency deviations).

To optimize the coefficients of the correlator, R4_DB7 and

R4_DB[8:9] must also be assigned. The value of these bits

depends on whether K is odd or even. These bits are assigned

according to Table 17 and Table 18.

Table 17. Assignment of Correlator K Value for 2FSK and 3FSK

K/2

(K + 1)/2

R4_DB7

R4_DB[8:9]

Even

N/A

Even

Odd

N/A

Odd

N/A

Even

Odd

N/A

Odd

Table 18. Assignment of Correlator K Value for 4FSK

R4_DB7

R4_DB[8:9]

Even

Odd

Linear Demodulator Setup

The linear demodulator can be used for 2FSK demodulation. To

enable the linear demodulator, set the DEMOD_SCHEME bits

(R4_DB[4:6]) to 000.

Post Demodulator Filter Setup

The 3 dB bandwidth of the post demodulator filter should be

set according to the received modulation type and data rate.

The bandwidth is controlled by R4_DB[20:29] and is given by

CLK

DEMOD

POST

CUTOFF

where fCUTOFF is the target 3 dB bandwidth in Hz of the post

demodulator filter.

Table 19. Post Demodulator Filter Bandwidth Settings for

2FSK/3FSK/4FSK Modulation Schemes

Received

Modulation

Post Demodulator Filter Bandwidth,

fCUTOFF (Hz)

2FSK

0.75 × data rate

3FSK

1 × data rate

4FSK

1.6 × symbol rate (= 0.8 × data rate)

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