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ADF7021 Datasheet(PDF) 11 Page - Analog Devices

Part # ADF7021
Description  High Performance Narrow-Band Transceiver IC
PDF  64 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADF7021 Datasheet(HTML) 11 Page - Analog Devices

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Data Sheet
ADF7021
Rev. B | Page 11 of 64
GENERAL SPECIFICATIONS
Table 5.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
TEMPERATURE RANGE (TA)
−40
+85
°C
POWER SUPPLIES
Voltage Supply, VDD
2.3
3.6
V
All VDD pins must be tied together
TRANSMIT CURRENT CONSUMPTION1
VDD = 3.0 V, PA is matched into 50 Ω
868 MHz
VCO_BIAS = 8
0 dBm
20.2
mA
5 dBm
24.7
mA
10 dBm
32.3
mA
450 MHz, Internal Inductor VCO
VCO_BIAS = 8
0 dBm
19.9
mA
5 dBm
23.2
mA
10 dBm
29.2
mA
426 MHz, External Inductor VCO
VCO_BIAS = 2
0 dBm
13.5
mA
5 dBm
17
mA
10 dBm
23.3
mA
RECEIVE CURRENT CONSUMPTION
VDD = 3.0 V
868 MHz
VCO_BIAS = 8
Low Current Mode
22.7
mA
High Sensitivity Mode
24.6
mA
433MHz, Internal Inductor VCO
VCO_BIAS = 8
Low Current Mode
24.5
mA
High Sensitivity Mode
26.4
mA
426 MHz, External Inductor VCO
VCO_BIAS = 2
Low Current Mode
17.5
mA
High Sensitivity Mode
19.5
mA
POWER-DOWN CURRENT CONSUMPTION
Low Power Sleep Mode
0.1
1
µA
CE low
1
The transmit current consumption tests used the same combined PA and LNA matching network as that used on the EVAL-ADF7021DBx evaluation boards. Improved
PA efficiency is achieved by using a separate PA matching network.
TIMING CHARACTERISTICS
VDD = 3 V ± 10%, DGND = AGND = 0 V, TA = 25°C, unless otherwise noted. Guaranteed by design but not production tested.
Table 6.
Parameter
Limit at TMIN to TMAX
Unit
Test Conditions/Comments
t1
>10
ns
SDATA to SCLK setup time
t2
>10
ns
SDATA to SCLK hold time
t3
>25
ns
SCLK high duration
t4
>25
ns
SCLK low duration
t5
>10
ns
SCLK to SLE setup time
t6
>20
ns
SLE pulse width
t8
<25
ns
SCLK to SREAD data valid, readback
t9
<25
ns
SREAD hold time after SCLK, readback
t10
>10
ns
SCLK to SLE disable time, readback
t11
5 < t11 < (¼ × tBIT)
ns
TxRxCLK negative edge to SLE
t12
>5
ns
TxRxDATA to TxRxCLK setup time (Tx mode)
t13
>5
ns
TxRxCLK to TxRxDATA hold time (Tx mode)
t14
>¼ × tBIT
µs
TxRxCLK negative edge to SLE
t15
>¼ × tBIT
µs
SLE positive edge to positive edge of TxRxCLK



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