ADF7021 datasheet(26/64 Pages) AD

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ADF7021

Data Sheet

Rev. B | Page 26 of 64

TRANSMITTER

RF OUTPUT STAGE

The power amplifier (PA) of the ADF7021 is based on a single-

ended, controlled current, open-drain amplifier that has been

designed to deliver up to 13 dBm into a 50 Ω load at a maximum

frequency of 950 MHz.

The PA output current and consequently, the output power, are

programmable over a wide range. The PA configuration is shown

in Figure 38. The output power is set using R2_DB[13:18].

IDAC

R2_DB(13:18)

R2_DB7

R2_DB(11:12)

RFGND

RFOUT

FROM VCO

R0_DB27

Figure 38. PA Configuration

The PA is equipped with overvoltage protection, which makes it

robust in severe mismatch conditions. Depending on the appli-

cation, users can design a matching network for the PA to exhibit

optimum efficiency at the desired radiated output power level

for a wide range of antennas, such as loop or monopole antennas.

See the LNA/PA Matching section for more information.

PA Ramping

When the PA is switched on or off quickly, its changing input

impedance momentarily disturbs the VCO output frequency.

This process is called VCO pulling, and it manifests as spectral

splatter or spurs in the output spectrum around the desired carrier

frequency. Some radio emissions regulations place limits on

these PA transient-induced spurs (for example, ETSI EN 300 220).

By gradually ramping the PA on and off, PA transient spurs are

minimized.

The ADF7021 has built-in PA ramping configurability. As

Figure 39 illustrates, there are eight ramp rate settings, defined

as a certain number of PA setting codes per one data bit period.

The PA steps through each of its 64 code levels but at different

speeds for each setting. The ramp rate is set by configuring

R2_DB[8:10].

If the PA is enabled/disabled by PA_ENABLE (R2_DB7), it

ramps up at the programmed rate but turns off hard. If the PA is

enabled/disabled by Tx/Rx (R0_DB27), it ramps up and down

at the programmed rate.

DATA BITS

PA RAMP 0

(NO RAMP)

PA RAMP 1

(256 CODES PER BIT)

PA RAMP 2

(128 CODES PER BIT)

PA RAMP 3

(64 CODES PER BIT)

PA RAMP 4

(32 CODES PER BIT)

PA RAMP 5

(16 CODES PER BIT)

PA RAMP 6

(8 CODES PER BIT)

PA RAMP 7

(4 CODES PER BIT)

...

Figure 39. PA Ramping Settings

PA Bias Currents

The PA_BIAS bits (R2_DB[11:12]) facilitate an adjustment of

the PA bias current to further extend the output power control

range, if necessary. If this feature is not required, the default

value of 9 µA is recommended. If output power of greater than

10 dBm is required, a PA bias setting of 11 µA is recommended.

The output stage is powered down by resetting R2_DB7.

MODULATION SCHEMES

The ADF7021 supports 2FSK, 3FSK, and 4FSK modulation.

The implementation of these modulation schemes is shown in

Figure 40.

VCO

÷N

THIRD-ORDER

Σ-Δ MODULATOR

PFD/

CHARGE

PUMP

REF

INTEGER-N

F_DEVIATION

PA STAGE

1 – D2 PR

SHAPING

4FSK

BIT SYMBOL

MAPPER

MUX

TxDATA

2FSK

4FSK

GAUSSIAN

RAISED COSINE

FILTERING

PRE-

CODER

3FSK

÷2

LOOP FILTER

FRAC_N

Figure 40. Transmit Modulation Implementation

ADF7021 Datasheet(PDF) 26 Page - Analog Devices

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