ADF7021 datasheet(22/64 Pages) AD

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ADF7021

Data Sheet

Rev. B | Page 22 of 64

FREQUENCY SYNTHESIZER

REFERENCE INPUT

The on-board crystal oscillator circuitry (see Figure 31) can

use a quartz crystal as the PLL reference. Using a quartz crystal

with a frequency tolerance of ≤10 ppm for narrow-band appli-

cations is recommended. It is possible to use a quartz crystal

with >10 ppm tolerance, but to comply with the absolute

frequency error specifications of narrow-band regulations

(for example, ARIB STD-T67 and ETSI EN 300-220), compen-

sation for the frequency error of the crystal is necessary.

The oscillator circuit is enabled by setting R1_DB12 high. It is

enabled by default on power-up and is disabled by bringing CE

low. Errors in the crystal can be corrected by using the automatic

frequency control feature or by adjusting the fractional-N value

(see the N Counter section).

OSC1

CP1

CP2

OSC2

Figure 31. Oscillator Circuit on the ADF7021

Two parallel resonant capacitors are required for oscillation at

the correct frequency. Their values are dependent upon the

crystal specification. They should be chosen to make sure that

the series value of capacitance added to the PCB track capacitance

adds up to the specified load capacitance of the crystal, usually

12 pF to 20 pF. Track capacitance values vary from 2 pF to 5 pF,

depending on board layout. When possible, choose capacitors

that have a very low temperature coefficient to ensure stable

frequency operation over all conditions.

Using a TCXO Reference

A single-ended reference (TCXO, VCXO, or OCXO) can also be

used with the ADF7021. This is recommended for applications

having absolute frequency accuracy requirements of <10 ppm, such

as ARIB STD-T67 or ETSI EN 300-220. There are two options

for interfacing the ADF7021 to an external reference oscillator.

•

An oscillator with CMOS output levels can be applied to

OSC2. The internal oscillator circuit should be disabled by

setting R1_DB12 low.

•

An oscillator with 0.8 V p-p levels can be ac-coupled through

a 22 pF capacitor into OSC1. The internal oscillator circuit

should be enabled by setting R1_DB12 high.

Programmable Crystal Bias Current

Bias current in the oscillator circuit can be configured

between 20 µA and 35 µA by writing to the XTAL_BIAS bits

(R1_DB[13:14]). Increasing the bias current allows the crystal

oscillator to power up faster.

CLKOUT Divider and Buffer

The CLKOUT circuit takes the reference clock signal from the

oscillator section, shown in Figure 31, and supplies a divided-

down, 50:50 mark-space signal to the CLKOUT pin. The CLKOUT

signal is inverted with respect to the reference clock. An even

divide from 2 to 30 is available. This divide number is set in

R1_DB[7:10]. On power-up, the CLKOUT defaults to divide-by-8.

DVDD

CLKOUT

ENABLE BIT

CLKOUT

OSC1

DIVIDER

1 TO 15

÷2

Figure 32. CLKOUT Stage

To disable CLKOUT, set the divide number to 0. The output

buffer can drive up to a 20 pF load with a 10% rise time at

4.8 MHz. Faster edges can result in some spurious feedthrough

to the output. A series resistor (1 kΩ) can be used to slow the

clock edges to reduce these spurs at the CLKOUT frequency.

R Counter

The 3-bit R counter divides the reference input frequency by an

integer of 1 to 7. The divided-down signal is presented as the

reference clock to the phase frequency detector (PFD). The divide

ratio is set in R1_DB[4:6]. Maximizing the PFD frequency reduces

the N value. This reduces the noise multiplied at a rate of 20 log(N)

to the output and reduces occurrences of spurious components.

PFD [Hz] = XTAL/R

Loop Filter

The loop filter integrates the current pulses from the charge

pump to form a voltage that tunes the output of the VCO to the

desired frequency. It also attenuates spurious levels generated by

the PLL. A typical loop filter design is shown in Figure 33.

CHARGE

PUMP OUT

VCO

Figure 33. Typical Loop Filter Configuration

The loop should be designed so that the loop bandwidth (LBW)

is approximately 100 kHz. This provides a good compromise

between in-band phase noise and out-of-band spurious rejection.

Widening the LBW excessively reduces the time spent jumping

between frequencies, but it can cause insufficient spurious attenua-

tion. Narrow-loop bandwidths can result in the loop taking long

periods to attain lock and can also result in a higher level of power

falling into the adjacent channel. The loop filter design on the

EVAL-ADF7021DBX should be used for optimum performance.

ADF7021 Datasheet(PDF) 22 Page - Analog Devices

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