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ADF7021 Datasheet(PDF) 50 Page - Analog Devices |
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ADF7021 Datasheet(HTML) 50 Page - Analog Devices |
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50 / 64 page  ADF7021 Data Sheet Rev. B | Page 50 of 64 REGISTER 3—TRANSMIT/RECEIVE CLOCK REGISTER FS8 0 0 . 1 1 FS7 0 0 . 1 1 FS3 0 0 . 1 1 ... ... ... ... ... ... FS2 0 1 . 1 1 FS1 1 0 . 0 1 CDR CLK DIVIDE 1 2 . 254 255 BK2 0 0 1 1 BK1 0 1 0 1 BBOS CLK DIVIDE 4 8 16 32 SK8 0 0 . 1 1 SK7 0 0 . 1 1 SK3 0 0 . 1 1 ... ... ... ... ... ... SK2 0 1 . 1 1 SK1 1 0 . 0 1 SEQ CLK DIVIDE 1 2 . 254 255 OK2 0 0 ... 1 OK1 0 1 ... 1 DEMOD CLK DIVIDE INVALID 1 ... 15 SEQUENCER_CLK_DIVIDE AGC_CLK_DIVIDE CDR_CLK_DIVIDE DEM_CLK_ DIVIDE ADDRESS BITS GD6 0 0 ... 1 GD5 0 0 ... 1 GD3 0 0 ... 1 GD4 0 0 ... 1 GD2 0 0 ... 1 GD1 0 1 ... 1 AGC CLK DIVIDE INVALID 1 ... 127 OK3 0 0 ... 1 0 0 ... 1 OK4 Figure 65. Register 3—Transmit/Receive Clock Register Map Baseband offset clock frequency (BBOS CLK) must be greater than 1 MHz and less than 2 MHz, where DIVIDE CLK BBOS XTAL CLK BBOS _ _ = Set the demodulator clock (DEMOD CLK) such that 2 MHz ≤ DEMOD CLK ≤ 15 MHz, where DIVIDE CLK DEMOD XTAL CLK DEMOD _ _ = For 2FSK/3FSK, the data/clock recovery frequency (CDR CLK) needs to be within 2% of (32 × data rate). For 4FSK, the CDR CLK needs to be within 2% of (32 × symbol rate). DIVIDE CLK CDR CLK DEMOD CLK CDR _ _ = The sequencer clock (SEQ CLK) supplies the clock to the digital receive block. It should be as close to 100 kHz as possible. DIVIDE CLK SEQ XTAL CLK SEQ _ _ = The time allowed for each AGC step to settle is determined by the AGC update rate. It should be set close to 10 kHz. DIVIDE CLK AGC CLK SEQ Rate Update AGC _ _ [Hz] = |
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