ADF7021 datasheet(33/64 Pages) AD

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Data Sheet

ADF7021

Rev. B | Page 33 of 64

Linear Demodulator

Figure 48 shows a block diagram of the linear demodulator.

SLICER

2FSK

FREQUENCY

LEVEL

LIMITER

LINEAR

DISCRIMINATOR

R4_DB(20:29)

FREQUENCY

READBACK

AND AFC LOOP

2FSK Rx DATA

RxCLK

Figure 48. Block Diagram of Linear FSK Demodulator

A digital frequency discriminator provides an output signal that

is linearly proportional to the frequency of the limiter outputs.

The discriminator output is filtered and averaged using a combined

averaging filter and envelope detector. The demodulated 2FSK

data from the post demodulator filter is recovered by threshold

detecting the envelope detector output, as shown in Figure 48.

This method of demodulation corrects for frequency errors

between transmitter and receiver when the received spectrum is

close to or within the IF bandwidth. This envelope detector

output is also used for AFC readback and provides the

frequency estimate for the AFC control loop.

Post Demodulator Filter

A second-order, digital low-pass filter removes excess noise from

the demodulated bit stream at the output of the discriminator.

The bandwidth of this post demodulator filter is programmable

and must be optimized for the user’s data rate and received

modulation type. If the bandwidth is set too narrow, performance

degrades due to intersymbol interference (ISI). If the bandwidth

is set too wide, excess noise degrades the performance of the

receiver. The POST_DEMODULATOR_BW bits (R4_DB[20:29])

set the bandwidth of this filter.

2FSK Bit Slicer/Threshold Detection

2FSK demodulation can be implemented using the correlator

FSK demodulator or the linear FSK demodulator. In both cases,

threshold detection is used for data recovery at the output of the

post demodulation filter.

The output signal levels of the correlator demodulator are

always centered about zero. Therefore, the slicer threshold level

can be fixed at zero, and the demodulator performance is

independent of the run-length constraints of the transmit data

bit stream. This results in robust data recovery that does not

suffer from the classic baseline wander problems that exist in

the more traditional FSK demodulators.

When the linear demodulator is used for 2FSK demodulation,

the output of the envelope detector is used as the slicer threshold,

and this output tracks frequency errors that are within the IF

filter bandwidth.

3FSK and 4FSK Threshold Detection

4FSK demodulation is implemented using the correlator

demodulator followed by the post demodulator filter and

threshold detection. The output of the post demodulation

filter is a 4-level signal that represents the transmitted symbols

(−3, −1, +1, +3). Threshold detection of 4FSK requires three

threshold settings, one that is always fixed at 0 and two that

are programmable and are symmetrically placed above and

below 0 using the 3FSK/4FSK_SLICER_THRESHOLD bits

(R13_DB[4:10]).

3FSK demodulation is implemented using the correlator demodu-

lator, followed by a post demodulator filter. The output of the

post demodulator filter is a 3-level signal that represents the

transmitted symbols (−1, 0, +1). Data recovery of 3FSK can be

implemented using threshold detection or Viterbi detection.

Threshold detection is implemented using two thresholds that

are programmable and are symmetrically placed above and

below zero using the 3FSK/4FSK_SLICER_THRESHOLD bits

(R13_DB[4:10]).

3FSK Viterbi Detection

Viterbi detection of 3FSK operates on a four-state trellis and is

implemented using two interleaved Viterbi detectors operating

at half the symbol rate. The Viterbi detector is enabled by

R13_DB11.

To facilitate different run length constraints in the transmitted

bit stream, the Viterbi path memory length is programmable

in steps of 4 bits, 6 bits, 8 bits, or 32 bits by setting the

VITERBI_PATH_MEMORY bits (R13_DB[13:14]). This

should be set equal to or longer than the maximum number

of consecutive 0s in the interleaved transmit bit stream.

When used with Viterbi detection, the receiver sensitivity

for 3FSK is typically +3 dB better than that obtained using

threshold detection. When the Viterbi detector is enabled,

however, the receiver bit latency is increased by twice the

Viterbi path memory length.

Clock Recovery

An oversampled digital clock and data recovery (CDR) PLL is

used to resynchronize the received bit stream to a local clock

in all modulation modes. The oversampled clock rate of the PLL

(CDR CLK) must be set at 32 times the symbol rate (see the

maximum data/symbol rate tolerance of the CDR PLL is

determined by the number of zero-crossing symbol transitions

in the transmitted packet. For example, if using 2FSK with a

101010 preamble, a maximum tolerance of ±3.0% of the data

rate is achieved. However, this tolerance is reduced during

recovery of the remainder of the packet where symbol transi-

tions may not be guaranteed to occur at regular intervals.

To maximize the data rate tolerance of the CDR, some form

of encoding and/or data scrambling is recommended that

guarantees a number of transitions at regular intervals. For

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