ADF7021 datasheet(16/64 Pages) AD

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ADF7021

Data Sheet

Rev. B | Page 16 of 64

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VCOIN

CREG1

VDD1

RFOUT

RFGND

RFIN

RFINB

RLNA

VDD4

RSET

CREG4

GND4

CLKOUT

TxRxCLK

TxRxDATA

SWD

VDD2

CREG2

ADCIN

GND2

SCLK

SREAD

SDATA

SLE

ADF7021

TOP VIEW

(Not to Scale)

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO GND.

Figure 10. Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Description

VCOIN

The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO).

The higher the tuning voltage, the higher the output frequency.

CREG1

Regulator Voltage for PA Block. Place a series 3.9 Ω resistor and a 100 nF capacitor between this pin and

ground for regulator stability and noise rejection.

VDD1

Voltage Supply for PA Block. Place decoupling capacitors of 0.1 μF and 100 pF as close as possible to this pin.

Tie all VDD pins together.

RFOUT

The modulated signal is available at this pin. Output power levels are from −16 dBm to +13 dBm. The output

should be impedance matched to the desired load using suitable components (see the Transmitter section).

RFGND

Ground for Output Stage of Transmitter. All GND pins should be tied together.

RFIN

LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA

input to ensure maximum power transfer (see the LNA/PA Matching section).

RFINB

Complementary LNA Input (see the LNA/PA Matching section).

RLNA

External Bias Resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.

VDD4

Voltage Supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor.

RSET

External Resistor. Sets charge pump current and some internal bias currents. Use a 3.6 kΩ resistor with 5% tolerance.

CREG4

Regulator Voltage for LNA/MIXER Block. Place a 100 nF capacitor between this pin and GND for regulator

stability and noise rejection.

12, 19, 22

GND4

Ground for LNA/MIXER Block.

13 to 18

MIX_I, MIX_I,

MIX_Q, MIX_Q,

FILT_I, FILT_I

Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected.

20, 21, 23

FILT_Q, FILT_Q,

TEST_A

Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected.

Chip Enable. Bringing CE low puts the ADF7021 into complete power-down. Register values are lost when CE

is low, and the part must be reprogrammed once CE is brought high.

SLE

Load Enable, CMOS Input. When SLE goes high, the data stored in the shift registers is loaded into one of the

four latches. A latch is selected using the control bits.

SDATA

Serial Data Input. The serial data is loaded MSB first with the 4 LSBs as the control bits. This pin is a high

impedance CMOS input.

SREAD

Serial Data Output. This pin is used to feed readback data from the ADF7021 to the microcontroller. The SCLK

input is used to clock each readback bit (for example, AFC or ADC) from the SREAD pin.

SCLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into

the 32-bit shift register on the CLK rising edge. This pin is a digital CMOS input.

ADF7021 Datasheet(PDF) 16 Page - Analog Devices

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