ADF7021 datasheet(46/64 Pages) AD

46 / 64 page

ADF7021

Data Sheet

Rev. B | Page 46 of 64

INTERFACING TO MICROCONTROLLER/DSP

Standard Transmit/Receive Data Interface

The standard transmit/receive signal and configuration interface

to a microcontroller is shown in Figure 58. In transmit mode,

the ADF7021 provides the data clock on the TxRxCLK pin, and

the TxRxDATA pin is used as the data input. The transmit data

is clocked into the ADF7021 on the rising edge of TxRxCLK.

MISO

ADuC84x

ADF7021

MOSI

SCLOCK

P3.7

P3.2/INT0

P2.4

P2.5

TxRxDATA

TxRxCLK

SWD

SREAD

SLE

P2.6

P2.7

SDATA

SCLK

GPIO

Figure 58. ADuC84x to ADF7021 Connection Diagram

In receive mode, the ADF7021 provides the synchronized data

clock on the TxRxCLK pin. The receive data is available on the

TxRxDATA pin. The rising edge of TxRxCLK should be used to

clock the receive data into the microcontroller. Refer to Figure 4

and Figure 5 for the relevant timing diagrams.

In 4FSK transmit mode, the MSB of the transmit symbol is

clocked into the ADF7021 on the first rising edge of the data

clock from the TxRxCLK pin. In 4FSK receive mode, the MSB

of the first payload symbol is clocked out on the first negative

edge of the data clock after the SWD, and should be clocked

into the microcontroller on the following rising edge. Refer to

Figure 6 and Figure 7 for the relevant timing diagrams.

UART Mode

In UART mode, the TxRxCLK pin is configured to input transmit

data in transmit mode. In receive mode, the receive data is available

on the TxRxDATA pin, thus providing an asynchronous data

interface. The UART mode can only be used with oversampled

2FSK. Figure 59 shows a possible interface to a microcontroller

using the UART mode of the ADF7021. To enable this UART

interface mode, set R0_DB28 high. Figure 8 and Figure 9 show

the relevant timing diagrams for UART mode.

UART

ADF7021

TxRxCLK

TxRxDATA

TxDATA

RxDATA

SWD

SREAD

SLE

SDATA

SCLK

GPIO

MICROCONTROLLER

Figure 59. ADF7021(UART Mode) to Asynchronous Microcontroller Interface

SPI Mode

In SPI mode, the TxRxCLK pin is configured to input transmit

data in transmit mode. In receive mode, the receive data is available

on the TxRxDATA pin. The data clock in both transmit and receive

modes is available on the CLKOUT pin. In transmit mode, data

is clocked into the ADF7021 on the positive edge of CLKOUT.

In receive mode, the TxRxDATA data pin should be sampled by

the microcontroller on the positive edge of the CLKOUT.

To enable SPI interface mode, set R0_DB28 high and set

R15_DB[17:19] to 0x7. Figure 8 and Figure 9 show the relevant

timing diagrams for SPI mode, while Figure 60 shows the

recommended interface to a microcontroller using the SPI

mode of the ADF7021.

SPI

ADF7021

TxRxCLK

TxRxDATA

MISO

MOSI

SWD

SREAD

SLE

SDATA

SCLK

GPIO

MICROCONTROLLER

SCLK

CLKOUT

Figure 60. ADF7021 (SPI Mode) to Microcontroller Interface

ADSP-BF533 interface

The suggested method of interfacing to the Blackfin® ADSP-

BF533 is given in Figure 61.

MOSI

ADSP-BF533

ADF7021

MISO

PF5

RSCLK1

DT1PRI

DR1PRI

RFS1

PF6

SDATA

SLE

TxRxDATA

SWD

SCK

SCLK

SREAD

TxRxCLK

Figure 61. ADSP-BF533 to ADF7021 Connection Diagram

ADF7021 Datasheet(PDF) 46 Page - Analog Devices

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