ADF7021 datasheet(23/64 Pages) AD

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Data Sheet

ADF7021

Rev. B | Page 23 of 64

The free design tool ADIsimPLL can also be used to design loop

filters for the ADF7021 (go to www.analog.com/ADIsimPLL for

details).

N Counter

The feedback divider in the ADF7021 PLL consists of an 8-bit

integer counter (R0_DB[19:26]) and a 15-bit Σ-Δ fractional_N

divider (R0_DB[4:18]). The integer counter is the standard

pulse-swallow type that is common in PLLs. This sets the

minimum integer divide value to 23. The fractional divide value

provides very fine resolution at the output, where the output

frequency of the PLL is calculated as



















Fractional

Integer

XTAL

OUT

When RF_DIVIDE_BY_2 (see the Voltage Controlled

Oscillator (VCO) section) is selected, this formula becomes



















0.5

Fractional

Integer_N

XTAL

OUT

The combination of the integer_N (maximum = 255) and

the fractional_N (maximum = 32,768/32,768) give a maximum

N divider of 255 + 1. Therefore, the minimum usable PFD is





255





Frequency

Output

Required

Maximum

PFD

MIN

For example, when operating in the European 868 MHz to

870 MHz band, PFDMIN equals 3.4 MHz.

VCO

4\N

THIRD-ORDER

Σ-∆ MODULATOR

PFD/

CHARGE

PUMP

4\R

INTEGER-N

FRACTIONAL-N

REFERENCE IN

Figure 34. Fractional-N PLL

Voltage Regulators

The ADF7021 contains four regulators to supply stable voltages

to the part. The nominal regulator voltage is 2.3 V. Regulator 1

requires a 3.9 Ω resistor and a 100 nF capacitor in series between

CREG1 and GND, whereas the other regulators require a 100 nF

capacitor connected between CREGx and GND. When CE is

high, the regulators and other associated circuitry are powered

on, drawing a total supply current of 2 mA. Bringing the CE pin

low disables the regulators, reduces the supply current to less

than 1 μA, and erases all values held in the registers. The serial

interface operates from a regulator supply. Therefore, to write to

the part, the user must have CE high and the regulator voltage

must be stabilized. Regulator status (CREG4) can be monitored

using the REGULATOR_READY signal from MUXOUT.

MUXOUT

The MUXOUT pin allows access to various digital points in the

ADF7021. The state of MUXOUT is controlled by R0_DB[29:31].

REGULATOR_READY

REGULATOR_READY is the default setting on MUXOUT

after the transceiver is powered up. The power-up time of

the regulator is typically 50 μs. Because the serial interface

is powered from the regulator, the regulator must be at its

nominal voltage before the ADF7021 can be programmed.

The status of the regulator can be monitored at MUXOUT.

When the regulator ready signal on MUXOUT is high,

programming of the ADF7021 can begin.

REGULATOR_READY (DEFAULT)

DIGITAL_LOCK_DETECT

RSSI_READY

Tx_Rx

LOGIC_ZERO

TRISTATE

MUX

CONTROL

DGND

DVDD

MUXOUT

FILTER_CAL_COMPLETE

LOGIC_ONE

Figure 35. MUXOUT Circuit

FILTER_CAL_COMPLETE

MUXOUT can be set to FILTER_CAL_COMPLETE. This signal

goes low for the duration of both a coarse IF filter calibration

and a fine IF filter calibration. It can be used as an interrupt to a

microcontroller to signal the end of the IF filter calibration.

DIGITAL_LOCK_DETECT

DIGITAL_LOCK_DETECT indicates when the PLL has locked.

The lock detect circuit is located at the PFD. When the phase

error on five consecutive cycles is less than 15 ns, lock detect is

set high. Lock detect remains high until a 25 ns phase error is

detected at the PFD.

RSSI_READY

MUXOUT can be set to RSSI_READY. This indicates that the

internal analog RSSI has settled and a digital RSSI readback

can be performed.

Tx_Rx

Tx_Rx signifies whether the ADF7021 is in transmit or receive

mode. When in transmit mode, this signal is low. When in

receive mode, this signal is high. It can be used to control an

external Tx/Rx switch.

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