ADF7021 datasheet(45/64 Pages) AD

45 / 64 page

Data Sheet

ADF7021

Rev. B | Page 45 of 64

SERIAL INTERFACE

The serial interface allows the user to program the 16-/32-bit

registers using a 3-wire interface (SCLK, SDATA, and SLE).

It consists of a level shifter, 32-bit shift register, and 16 latches.

Signals should be CMOS compatible. The serial interface is

Data is clocked into the register, MSB first, on the rising edge of

each clock (SCLK). Data is transferred to one of 16 latches on the

rising edge of SLE. The destination latch is determined by the

value of the four control bits (C4 to C1); these are the bottom

4 LSBs, DB3 to DB0, as shown in Figure 2. Data can also be read

back on the SREAD pin.

READBACK FORMAT

The readback operation is initiated by writing a valid control

word to the readback register and enabling the READBACK bit

(R7_DB8 = 1). The readback can begin after the control word

has been latched with the SLE signal. SLE must be kept high

while the data is being read out. Each active edge at the SCLK

pin successively clocks the readback word out at the SREAD

pin, as shown in Figure 57, starting with the MSB first. The data

appearing at the first clock cycle following the latch operation

must be ignored. An extra clock cycle is needed after the 16th

readback bit to return the SREAD pin to tristate. Therefore, 18

total clock cycles are needed for each read back. After the 18th

clock cycle, SLE should be brought low.

AFC Readback

The AFC readback is valid only during the reception of FSK

signals with either the linear or correlator demodulator active.

The AFC readback value is formatted as a signed 16-bit integer

comprising Bit RV1 to Bit RV16 and is scaled according to the

following formula:

FREQ RB [Hz] = (AFC_READBACK × DEMOD CLK)/218

In the absence of frequency errors, FREQ RB is equal to the IF

frequency of 100 kHz. Note that, for the AFC readback to yield

a valid result, the down converted input signal must not fall outside

the bandwidth of the analog IF filter. At low input signal levels,

the variation in the readback value can be improved by averaging.

RSSI Readback

The format of the readback word is shown in Figure 57. It

comprises the RSSI-level information (Bit RV1 to Bit RV7), the

current filter gain (FG1, FG2), and the current LNA gain (LG1,

LG2) setting. The filter and LNA gain are coded in accordance

with the definitions in the Register 9—AGC Register section. For

signal levels below −100 dBm, averaging the measured RSSI values

improves accuracy. The input power can be calculated from the

RSSI readback value as outlined in the RSSI/AGC section.

Battery Voltage/ADCIN/Temperature Sensor Readback

The battery voltage is measured at Pin VDD4. The readback

information is contained in Bit RV1 to Bit RV7. This also

applies for the readback of the voltage at the ADCIN pin and

the temperature sensor. From the readback information, the

battery or ADCIN voltage can be determined using

VBATTERY = (BATTERY_VOLTAGE_READBACK)/21.1

VADCIN = (ADCIN_VOLTAGE_READBACK)/42.1

The temperature can be calculated using

Temp [°C] = −40 + (68.4 − TEMP_READBACK) × 9.32

Silicon Revision Readback

The silicon revision readback word is valid without setting any

other registers. The silicon revision word is coded with four

quartets in BCD format. The product code (PC) is coded with

three quartets extending from Bit RV5 to Bit RV16. The revision

code (RC) is coded with one quartet extending from Bit RV1 to

Bit RV4. The product code for the ADF7021 should read back

as PC = 0x210. The current revision code should read as RC = 0x4.

Filter Bandwidth Calibration Readback

The filter calibration readback word is contained in Bit RV1 to

Bit RV8. This readback can be used for manual filter adjust, thereby

avoiding the need to do an IF filter calibration in some instances.

The manual adjust value is programmed by R5_DB[14:19]. To

calculate the manual adjust based on a filter calibration readback,

use the following formula:

IF_FILTER_ADJUST = FILTER_CAL_READBACK − 128

The result should be programmed into R5_DB[14:19] as outlined

in the Register 5—IF Filter Setup Register section.

READBACK MODE

AFC READBACK

DB15

RV16

RSSI READBACK

BATTERY VOLTAGE/ADCIN/

TEMP. SENSOR READBACK

SILICON REVISION

FILTER CAL READBACK

READBACK VALUE

DB14

RV15

DB13

RV14

DB12

RV13

DB11

RV12

DB10

RV11

LG2

RV11

DB9

RV10

LG1

RV10

DB8

RV9

FG2

RV9

DB7

RV8

FG1

RV8

DB6

RV7

DB5

RV6

DB4

RV5

DB3

RV4

DB2

RV3

DB1

RV2

DB0

RV1

Figure 57. Readback Value Table

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