HEATEVM datasheet(63/79 Pages) TI1

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Data Valid

SCICLK

SCITX

SCIRX

tc(SCC)

tw(SCCH)

tw(SCCL)

td(SCCH TXV)

tv(TX)

tsu(RX SCCL)

tv(SCCL RX)

SM470R1B1M-HT

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SPNS155H – SEPTEMBER 2009 – REVISED SEPTEMBER 2013

SCIn ISOSYNCHRONOUS MODE TIMINGS - EXTERNAL CLOCK

Timing Requirements for External Clock SCIn Isosynchronous Mode

(1) (2) (3)

(see Figure 21)

MIN

MAX

UNIT

tc(SCC)

Cycle time, SCInCLK(4)

8tc(ICLK)

tw(SCCH)

Pulse duration, SCInCLK high

0.5tc(SCC) – 0.25tc(ICLK)

0.5tc(SCC) + 0.25tc(ICLK)

tw(SCCL)

Pulse duration, SCInCLK low

0.5tc(SCC) – 0.25tc(ICLK)

0.5tc(SCC) + 0.25tc(ICLK)

td(SCCH-TXV)

Delay time, SCInCLK high to SCInTX valid

2tc(ICLK) + 12 + t r

tv(TX)

Valid time, SCInTX data after SCInCLK low

2tc(SCC) – 10

tsu(RX-SCCL)

Setup time, SCInRX before SCInCLK low

tv(SCCL-RX)

Valid time, SCInRX data after SCInCLK low

2tc(ICLK) + 10

(1)

Not production tested.

(2)

tc(ICLK) = interface clock cycle time = 1/f(ICLK)

(3)

For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.

(4)

When driving an external SCInCLK, the following must be true: tc(SCC) ≥ 8tc(ICLK).

Data transmission / reception characteristics for isosynchronous mode with external clocking are similar to the

asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the SCICLK

falling edge.

Figure 21. SCIn Isosynchronous Mode Timing Diagram for External Clock

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