HEATEVM datasheet(11/79 Pages) TI1

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SM470R1B1M-HT

www.ti.com

SPNS155H – SEPTEMBER 2009 – REVISED SEPTEMBER 2013

DESCRIPTION

The SM470R1B1M (1) devices are members of the Texas Instruments SM470R1x family of general-purpose

16/32-bit reduced instruction set computer (RISC) microcontrollers. The B1M microcontroller offers high

performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a

high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views

memory as a linear collection of bytes numbered upwards from zero. The SM470R1B1M utilizes the big-endian

format where the most significant byte of a word is stored at the lowest numbered byte and the least significant

byte at the highest numbered byte.

High-end embedded control applications demand more performance from their controllers while maintaining low

costs. The B1M RISC core architecture offers solutions to these performance and cost demands while

maintaining low power consumption.

The B1M devices contain the following:

•

ARM7TDMI 16/32-Bit RISC CPU

•

SM470R1x system module (SYS) with 470+ enhancements

•

1M-byte flash

•

64K-byte SRAM

•

Zero-pin phase-locked loop (ZPLL) clock module

•

Digital watchdog (DWD) timer

•

Analog watchdog (AWD) timer

•

Enhanced real-time interrupt ( RTI) module

•

Interrupt expansion module (IEM)

•

Memory security module (MSM)

•

JTAG security module

•

Two serial peripheral interface (SPI) modules

•

Three serial communications interface (SCI) modules

•

Two high-end CAN controllers (HECC)

•

Five inter-integrated circuit (I2C) modules

•

10-bit multi-buffered analog-to-digital converter (MibADC), with 12 input channels

•

High-end timer lite (HET) controlling 12 I/Os

•

External clock prescale (ECP)

•

Expansion bus module (EBM)

•

Up to 93 I/O pins

The functions performed by the 470+ system module (SYS) include:

•

Address decoding

•

Memory protection

•

Memory and peripherals bus supervision

•

Reset and abort exception management

•

Prioritization for all internal interrupt sources

•

Device clock control

•

Parallel signature analysis (PSA)

The enhanced real-time interrupt (RTI) module on the B1M has the option to be driven by the oscillator clock.

The digital watchdog (DWD) is a 25-bit resettable decrementing counter that provides a system reset when the

watchdog counter expires. This data sheet includes device-specific information such as memory and peripheral

select assignment, interrupt priority, and a device memory map. For a more detailed functional description of the

SYS module, see the TMS470R1x System Module Reference Guide (literature number SPNU189).

The B1M memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-

word, and word modes.

(1)

Throughout the remainder of this document, the SM470R1B1M will be referred to as either the full device name or as B1M.

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