Electronic Components Datasheet Search
  English  ▼

X  

HEATEVM Datasheet(PDF) 64 Page - Texas Instruments

Part # HEATEVM
Description  16/32-BIT RISC FLASH MICROCONTROLLER
PDF  79 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

HEATEVM Datasheet(HTML) 64 Page - Texas Instruments

Back Button HEATEVM Datasheet HTML 60Page - Texas Instruments HEATEVM Datasheet HTML 61Page - Texas Instruments HEATEVM Datasheet HTML 62Page - Texas Instruments HEATEVM Datasheet HTML 63Page - Texas Instruments HEATEVM Datasheet HTML 64Page - Texas Instruments HEATEVM Datasheet HTML 65Page - Texas Instruments HEATEVM Datasheet HTML 66Page - Texas Instruments HEATEVM Datasheet HTML 67Page - Texas Instruments HEATEVM Datasheet HTML 68Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 64 / 79 page
background image
SM470R1B1M-HT
SPNS155H – SEPTEMBER 2009 – REVISED SEPTEMBER 2013
www.ti.com
I2C TIMING
I2C Signals (SDA and SCL) Switching Characteristics(5)(6) Assumes testing over recommended operating
conditions.
I2C Signals (SDA and SCL) Switching Characteristics
(1) (2)
STANDARD MODE
FAST MODE
PARAMETER
UNIT
MIN
MAX
MIN
MAX
tc(I2CCLK)
Cycle time, I2C module clock
75
150
75
150
ns
tc(SCL)
Cycle time, SCL
10
2.5
µs
Setup time, SCL high before SDA low (for a repeated START
tsu(SCLH-SDAL)
4.7
0.6
µs
condition)
Hold time, SCL low after SDA low (for a repeated START
th(SCLL-SDAL)
4
0.6
µs
condition)
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
µs
tw(SCLH)
Pulse duration, SCL high
4
0.6
µs
tsu(SDA-SCLH)
Setup time, SDA valid before SCL high
250
100
ns
th(SDA-SCLL)
Hold time, SDA valid after SCL low
For I2C bus devices
0
3.45(3)
0
0.9
µs
tw(SDAH)
Pulse duration, SDA high between STOP and START conditions
4.7
1.3
µs
tr(SCL)
Rise time, SCL
1000
20+0.1Cb
(4)
300
ns
tr(SDA)
Rise time, SDA
1000
20+0.1Cb
(4)
300
ns
tf(SCL)
Fall time, SCL
300
20+0.1Cb
(4)
300
ns
tf(SDA)
Fall time, SDA
300
20+0.1Cb
(4)
300
ns
tsu(SCLH-SDAH)
Setup time, SCL high before SDA high (for STOP condition)
4.0
0.6
µs
tw(SP)
Pulse duration, spike (must be suppressed)
0
50
ns
Cb
(4)
Capacitive load for each bus line
400
400
pF
(5)
Not production tested.
(6)
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(1)
Not production tested.
(2)
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(3)
The maximum th(SDA-SCLL) for I2C bus devices needs to be met only if the device does not stretch the low period (tw(SCLL)) of the SCL
signal.
(4)
C b = The total capacitance of one bus line in pF. If mixed with HS=mode devices, faster fall-times are allowed.
64
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com