HEATEVM datasheet(13/79 Pages) TI1

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SM470R1B1M-HT

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SPNS155H – SEPTEMBER 2009 – REVISED SEPTEMBER 2013

The B1M device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous

external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the

peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the

TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202).

Device Characteristics

Table 3 identifies all the characteristics of the B1M device except the SYSTEM and CPU, which are generic.

Table 3. Device Characteristics

DEVICE DESCRIPTION

CHARACTERISTICS

COMMENTS

SM470R1B1M

MEMORY

For the number of memory selects on this device, see Table 6, SM470R1B1M Memory Selection Assignment.

Pipeline/Non-Pipeline

Flash is pipeline-capable.

1M-Byte flash

The B1M RAM is implemented in one 64K array selected by two

INTERNAL MEMORY

64K-Byte SRAM

memory-select signals (see Table 6, SM470R1B1M Memory

Selection Assignment ).

Memory Security Module (MSM)

JTAG Security Module

PERIPHERALS

For the device-specific interrupt priority configurations, see Table 9, Interrupt Priority. And for the 1K peripheral address ranges and their

peripheral selects, see Table 7, B1M Peripherals, System Module, and Flash Base Addresses.

CLOCK

ZPLL

Zero-pin PLL has no external loop filter pins.

Expansion Bus

Expansion bus module with 42 pins. Supports 8- and 16-bit

EBM

memories. See Table 10 for details.

GENERAL-PURPOSE I/Os

Port A has 8 external pins; Port B has only 1 external pin; Port C has

46 I/O

5 external pins; Port D has 6 external pins; Ports E, F, and G each

have 8 external pins; and Port H has 2 external pins.

ECP

YES

SCI

3 (3-pin)

CAN (HECC and/or SCC)

2 HECC

Two high-end CAN controllers

SPI (5-pin, 4-pin or 3-pin)

2 (5-pin)

I2C

The high-resolution (HR) SHARE feature allows even-numbered HR

pins to share the next higher odd-numbered HR pin structures. This

HR sharing is independent of whether or not the odd pin is available

HET with XOR Share

12 I/O

externally. If an odd pin is available externally and shared, then the

odd pin can only be used as a general-purpose I/O. For more

information on HR SHARE, see the TMS470R1x High-End Timer

(HET) Reference Guide (literature number SPNU199).

HET RAM

64-Instruction Capacity

10-bit, 12-channel

Both the logic and registers for a full 16-channel MibADC are

MibADC

64-word FIFO

present.

CORE VOLTAGE

1.8 V

I/O VOLTAGE

3.3 V

PINS

84 or 144

PACKAGES

HFQ, HKP or PGE

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