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HEATEVM Datasheet(PDF) 71 Page - Texas Instruments |
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HEATEVM Datasheet(HTML) 71 Page - Texas Instruments |
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71 / 79 page ![]() 0 1 2 3 4 5 0 ... 101 0 ... 100 0 ... 011 0 ... 010 0 ... 001 0 ... 000 0 ... 110 Analog Input Value (LSB) 1 LSB 1 LSB 0 1 2 3 4 5 0 ... 101 0 ... 100 0 ... 011 0 ... 010 0 ... 001 0 ... 000 0 ... 110 1 LSB 1 LSB Differential Linearity Error(- 1/2 LSB) Differential Linearity Error(1/2 LSB) Parasitic Capacitance Vsrc Ri MibADC Input Pin Rs Sample Capacitor Ci Rleak Sample Switch External SM470R1B1M-HT www.ti.com SPNS155H – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 Figure 25. MibADC Input Equivalent Circuit Table 16. Multi-Buffer ADC Timing Requirements(1) MIN NOM MAX UNIT tc(ADCLK) Cycle time, MibADC clock 0.067 µs td(SH) Delay time, sample and hold time 1 µs td©) Delay time, conversion time 0.55 µs td(SHC) (2) Delay time, total sample/hold and conversion time 1.55 µs (1) Not production tested. (2) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors; for more details, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206). The differential nonlinearity error shown in Figure 26 (sometimes referred to as differential linearity) is the difference between an actual step width and the ideal value of 1 LSB. A. 1 LSB = (ADREFHI - ADREFLO)/2 10 Figure 26. Differential Nonlinearity (DNL) Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 71 |
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