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GMS81C2012 Datasheet(PDF) 63 Page - Hynix Semiconductor

Part # GMS81C2012
Description  CMOS Single-Chip 8-Bit Microcontroller with A/D Converter & VFD Driver
PDF  92 Pages
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

GMS81C2012 Datasheet(HTML) 63 Page - Hynix Semiconductor

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Hyundai Micro Electronics
GMS81C2020/GMS81C2120
Nov. 1999 Ver 0.0
preliminary
63
18. ANALOG TO DIGITAL CONVERTER
The analog-to-digital converter (A/D) allows conversion
of an analog input signal to a corresponding 8-bit digital
value. The A/D module has twelve analog inputs, which
are multiplexed into one sample and hold. The output of
the sample and hold is the input into the converter, which
generates the result via successive approximation.
The A/D module has two registers which are the control
register ADCM and A/D result register ADCR. The
ADCM register, shown in Figure 18-2 , controls the oper-
ation of the A/D converter module. The port pins can be
configured as analog inputs or digital I/O.
To use analog inputs, each port is assigned analog input
port by setting the bit ANSEL[7:0] in R6FUNC register.
Also it is assigned analog input port by setting the bit AN-
SEL[11:8] in R7FUNC register. And selected the corre-
sponding channel to be converted by setting ADS[3:0].
The processing of conversion is start when the start bit
ADST is set to "1". After one cycle, it is cleared by hard-
ware. The register ADCR contains the results of the A/D
conversion. When the conversion is completed, the result
is loaded into the ADCR, the A/D conversion status bit
ADSF is set to "1", and the A/D interrupt flag ADIF is set.
The block diagram of the A/D module is shown in Figure
18-1 . The A/D status bit ADSF is set automatically when
A/D conversion is completed, cleared when A/D conver-
sion is in process. The conversion time takes maximum 20
uS (at fXI=4 MHz).
Figure 18-1 A/D Converter Block Diagram
R67/AN7
ANSEL7
0111
AVDD
ADEN
S/H
Successive
Approximation
Circuit
A D IF
Resistor
Ladder
Circuit
ADS[3:0]
ADCR(8-bit)
Sample & Hold
A/D Interrupt
ADDRESS : EBH
RESET VALUE : Undefined
A/D Result Register
R7FUNC[3:0]
R6FUNC[7:0]
R66/AN6
ANSEL6
0110
R65/AN5
ANSEL5
0101
R64/AN4
ANSEL4
0100
R63/AN3
ANSEL3
0011
R62/AN2
ANSEL2
0010
R61/AN1
ANSEL1
0001
R60/AN0
ANSEL0
0000
R73/AN11
ANSEL11
1011
R72/AN10
ANSEL10
1010
R71/AN9
ANSEL9
1001
R70/AN8
ANSEL8
1000
[ADCM.6]
COMPARATOR



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