GMS81C2012 datasheet(66/92 Pages) HYNIX

66 / 92 page

GMS81C2020/GMS81C2120

Hyundai Micro Electro nics

preliminary

Nov. 1999 Ver 0.0

19. INTERRUPTS

The GMS81C2020 and GMS81C2120 interrupt circuits

consist of Interrupt enable register (IENH, IENL), Inter-

rupt request flags of IRQH, IRQL, Interrupt Edge Selec-

tion Register (IEDS), priority circuit and Master enable

flag("I" flag of PSW). The configuration of interrupt cir-

cuit is shown in Figure and Interrupt priority is shown in

Table 19-1 .

The External Interrupts INT0 and INT1 can each be transi-

tion-activated (1-to-0, 0-to-1 and both transiton).

The flags that actually generate these interrupts are bit

INT0IF and INT1IF in Register IRQH. When an external

interrupt is generated, the flag that generated it is cleared

by the hardware when the service routine is vectored to

only if the interrupt was transition-activated.

The Timer 0 and Timer 1 Interrupts are generated by T0IF

and T1IF, which are set by a match in their respective tim-

er/counter register. The AD converter Interrupt is generat-

ed by ADIF which is set by finishing the analog to digital

conversion. The Watch dog timer Interrupt is generated by

WDTIF which set by a match in Watch dog timer register

(when the bit WDTON is set to "0"). The Basic Interval

Timer Interrupt is generated by BITIF which is set by a

overflowing of the Basic Interval Timer Register(BITR).

The Serial Peripheral Interface (SPI) is generated by SPIIF

which is set by communicating with other peripheral of mi-

crocontroller devices (by finishing the data transmission).

Figure 19-1 Block Diagram of Interrupt Function

BIT

BITIF

WDTIF

WDT

A/D Converter

Timer 1

Timer 0

External Int. 1

External Int. 0

IENH[7:4]

Interrupt Enable

IRQH[7:4]

IRQL

Interrupt

Vector

Address

Generator

Internal bus line

Release STOP

To CPU

Interrupt Master

Enable Flag[PSW.2]

I Flag

IENL[7:4]

Priority

I-flag is in PSW, it is cleared by "DI", set by

"EI" instruction.When it goes interrupt service,

I-flag is cleared by hardware, thus any other

interrupt are inhibited. When interrupt service is

completed by "RETI" instruction, I-flag is set to

"1" by hardware.

INT0IF

INT1IF

T0IF

T1IF

ADIF

SPI

SPIIF

IEDS[3:0]

IRQL[7:4]

IRQH

Control

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