80960CF-30 datasheet(8/62 Pages) INTEL

8 / 62 page

SPECIAL ENVIRONMENT 80960CF-30 -25 -16

PACKAGE INFORMATION

Package Introduction

This section describes the pins pinouts and thermal

characteristics for the 80960CF in the 168-pin Ce-

ramic Pin Grid Array (PGA) package For complete

package specifications and information see the Intel

Packaging Outlines and Dimensions Guide (Order

No 231369)

Pin Descriptions

The 80960CF pins are described in this section Ta-

ble 1 presents the legend for interpreting the pin de-

scriptions in the following tables

Pins associated with the 32-bit demultiplexed proc-

essor bus are described in Table 2 Pins associated

with basic processor configuration and control are

described in Table 3

Pins associated with the

80960CF DMA Controller and Interrupt Unit are de-

scribed in Table 4

Figure 3 provides an example pin description table

entry ‘‘IO’’ signifies that data pins are input-output

‘‘S’’ indicates pins are synchronous to PCLK21

‘‘H(Z)’’ indicates that these pins float while the proc-

essor bus is in a Hold Acknowledge state ‘‘R(Z)’’

indicates that the pins also float while RESET is low

All pins float while the processor is in the ONCE

mode

Table 1 Pin Description Nomenclature

Symbol

Description

Input only pin

Output only pin

Pin can be either an input or output

Pins ‘‘must be’’ connected as

described

S()

Synchronous Inputs must meet setup

and hold times relative to PCLK21 for

proper operation All outputs are

synchronous to PCLK21

S(E) Edge sensitive input

S(L) Level sensitive input

A()

Asynchronous Inputs may be

asynchronous to PCLK21

A(E) Edge sensitive input

A(L) Level sensitive input

H()

While the processor’s bus is in the

Hold Acknowledge or Bus Backoff

state the pin

H(1)

is driven to VCC

H(0)

is driven to VSS

H(Z)

floats

H(Q)

continues to be a valid output

R()

While the processor’s RESET pin is

low the pin

R(1)

is driven to VCC

R(0)

is driven to VSS

R(Z)

floats

R(Q)

continues to be a valid output

Name

Type

Description

D310

DATA BUS

carries 32- 16- or 8-bit data quantities depending on bus width configuration

The least significant bit of the data is carried on D0 and the most significant on D31 When

S(L)

the bus is configured for 8-bit data the lower 8 data lines D70 are used For 16-bit bus

H(Z)

widths D150 are used For 32-bit bus widths the full data bus is used

R(Z)

Figure 3 Example Pin Description Entry

80960CF-30 Datasheet(PDF) 8 Page - Intel Corporation

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