80960CF-30 datasheet(12/62 Pages) INTEL

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SPECIAL ENVIRONMENT 80960CF-30 -25 -16

Table 3 80960CF Pin DescriptionProcessor Control Signals

(Continued)

Name

Type

Description

STEST

SELF TEST

causes the processor’s internal self-test feature to be enabled or

disabled at initialization STEST is read on the rising edge of RESET When asserted

S(L)

the processor’s internal self-test and external bus confidence tests are performed

H(Z)

during processor initialization When deasserted only the external bus confidence

R(Z)

tests are performed during initialization

ONCE

ON CIRCUIT EMULATION

causes all outputs to be floated when asserted ONCE is

continuously sampled while RESET is low and is latched on the rising edge of

A(L)

RESET To place the processor in the ONCE state

H(Z)

(1)

assert RESET and ONCE (order does not matter)

R(Z)

(2)

wait for at least 16 CLKIN periods in 2-x mode or 10000 CLKIN periods in 1-x

mode after VCC and CLKIN are within operating specifications

(3)

deassert RESET

(4)

wait at least 32 CLKIN periods

(The processor is now latched in the ONCE state as long as RESET is high)

To exit the ONCE state bring VCC and CLKIN to operating conditions then assert

RESET and bring ONCE high prior to deasserting RESET

CLKIN must operate within the specified operating conditions of the processor until

step 4 above is completed The CLKIN may then be changed to DC to achieve the

lowest possible ONCE mode leakage current

ONCE can be used by emulator products or for board testers to effectively make an

installed processor transparent in the board

CLKIN

CLOCK INPUT

is an input for the external clock needed to run the processor The

external clock is internally divided as prescribed by the CLKMODE pin to produce

A(E)

PCLK21

H(Z)

R(Z)

CLKMODE

CLOCK MODE

selects the division factor applied to the external clock input (CLKIN)

When CLKMODE is high CLKIN is divided by one to create PCLK21 and the

A(L)

processor’s internal clock When CLKMODE is low CLKIN is divided by two to create

H(Z)

PCLK21 and the processor’s internal clock CLKMODE should be tied high or low in

R(Z)

a system as the clock mode is not latched by the processor If left unconnected the

processor internally pulls the CLKMODE pin low enabling the 2-x clock mode

PCLK2

PROCESSOR OUTPUT CLOCKS

provide a timing reference for all inputs and

outputs of the processor All inputs and output timings are specified in relation to

PCLK1

PCLK2 and PCLK1 PCLK2 and PCLK1 are identical signals Two output pins are

H(Q)

provided to allow flexibility in the system’s allocation of capacitive loading on the

R(Q)

clock PCLK21 may also be connected at the processor to form a single clock signal

VSS

GROUND

connections consist of 24 pins which must be connected externally to a

VSS board plane

VCC

POWER

connections consist of 24 pins which must be connected externally to a VCC

board plane

VCCPLL

VCCPLL is a separate VCC supply pin for the phase lock loop used in 1x clock mode

Connecting a simple low pass filter to VCCPLL may help reduce clock jitter (TCP)in

noisy environments Otherwise VCCPLL should be connected to VCC

NO CONNECT

pins must not be connected in a system

80960CF-30 Datasheet(PDF) 12 Page - Intel Corporation

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