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80960CF-30 Datasheet(PDF) 14 Page - Intel Corporation |
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80960CF-30 Datasheet(HTML) 14 Page - Intel Corporation |
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14 / 62 page  SPECIAL ENVIRONMENT 80960CF-30 -25 -16 33 80960CF Pinout 331 80960CF PGA PINOUT Tables 5 and 6 list the 80960CF pin names with package location Figure 4-a depicts the complete 80960CF pinout as viewed from the top side of the component (ie pins facing down) Figure 4b shows the complete 80960CF pinout as viewed from the pin-side of the package (ie pins facing up) See Section 40 Electrical Specifications for specifica- tions and recommended connections Table 5 PGA Pin Name with Package Location (Signal Order) Address Bus Data Bus Bus Control Processor Control IO Name Location Name Location Name Location Name Location Name Location A31 S15 D31 R03 BE3 S05 RESET A16 DREQ3 A07 A30 Q13 D30 Q05 BE2 S06 DREQ2 B06 A29 R14 D29 S02 BE1 S07 FAIL A02 DREQ1 A06 A28 Q14 D28 Q04 BE0 R09 DREQ0 B05 A27 S16 D27 R02 STEST B02 A26 R15 D26 Q03 WR S10 DACK3 A10 A25 S17 D25 S01 ONCE C03 DACK2 A09 A24 Q15 D24 R01 ADS R06 DACK1 A08 A23 R16 D23 Q02 CKLIN C13 DACK0 B08 A22 R17 D22 P03 READY S03 CLKMODE C14 A21 Q16 D21 Q01 BTERM R04 PCLK1 B14 EOP TC0 A11 A20 P15 D20 P02 PCLK2 B13 EOP TC1 A12 A19 P16 D19 P01 WAIT S12 EOP TC2 A13 A18 Q17 D18 N02 BLAST S08 VSS EOP TC3 A14 A17 P17 D17 N01 Location A16 N16 D16 M01 DTR S11 C07 C08 C09 XINT7 C17 C10 C11 C12 A15 N17 D15 L01 DEN S09 XINT6 C16 F15 G03 G15 A14 M17 D14 L02 XINT5 B17 H03 H15 J03 J15 K03 K15 A13 L16 D13 K01 LOCK S14 XINT4 C15 L03 L15 M03 A12 L17 D12 J01 XINT3 B16 M15 Q07 Q08 Q09 Q10 Q11 A11 K17 D11 H01 HOLD R05 XINT2 A17 A10 J17 D10 H02 HOLDA S04 VCC XINT1 A15 A9 H17 D9 G01 BREQ R13 Location XINT0 B15 A8 G17 D8 F01 B07 B09 B11 B12 C06 A7 G16 D7 E01 DC S13 NMI D15 E15 F03 F16 A6 F17 D6 F02 DMA R12 G02 H16 J02 J16 K02 K16 M02 A5 E17 D5 D01 SUP Q12 M16 N03 N15 A4 E16 D4 E02 Q06 R07 R08 R10 R11 VCCPLL B10 A3 D17 D3 C01 BOFF B01 No Connect A2 D16 D2 D02 Location D1 C02 A01 A03 A04 A05 B03 B04 C04 C05 D03 D0 E03 14 |
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