80960CF-30 datasheet(5/62 Pages) INTEL

5 / 62 page

SPECIAL ENVIRONMENT 80960CF-30 -25 -16

PURPOSE

This document previews electrical characterizations

of Intel’s i960 CF embedded microprocessor (avail-

able in 33 25 and 16 MHz) For a detailed descrip-

tion of any i960 CF processor functional topicoth-

er than parametric performancerefer to the latest

i960 CA Microprocessor Reference Manual (Order

No 270710) and the

i960 CF Reference Manual Ad-

dendum (Order No 272188)

i960 CF PROCESSOR OVERVIEW

Intel’s i960 CF microprocessor is the performance

follow-on product to the i960 CA processor The

i960 CF product is socket- and object code-compati-

ble with the CA this makes CA-to-CF design up-

grades straightforward The i960 CF processor’s in-

struction cache is 4 Kbytes (CA device has 1 Kbyte)

CF data cache is 1 Kbyte (CA device has no data

cache) This extra cache on the CF product adds a

significant performance boost over the CA The

80960CF is object code compatible with the 32-bit

80960 Core Architecture while including Special

Function Register extensions to control on-chip pe-

ripherals and instruction set extensions to shift 64-

bit operands and configure on-chip hardware Multi-

ple 128-bit internal busses on-chip instruction cach-

ing and a sophisticated instruction scheduler allow

the processor to sustain execution of two instruc-

tions every clock and peak at execution of three

instructions per clock

A 32-bit demultiplexed and pipelined burst bus pro-

vides a 132 Mbytes bandwidth to a system’s high-

speed external memory sub-system In addition the

80960CF’s on-chip caching of instructions proce-

dure context and critical program data substantially

decouples system performance from the wait states

associated with accesses to the system’s slower

cost sensitive main memory sub-system

The 80960CF bus controller also integrates full wait

state and bus width control for highest system per-

formance with minimal system design complexity

Unaligned access and Big Endian byte order support

reduces the cost of porting existing applications to

the 80960CF

The processor also integrates four complete data-

chaining DMA channels and a high-speed interrupt

controller on-chip The DMA channels perform sin-

gle-cycle or two-cycle transfers data packing and

unpacking and data chaining Block transfers in ad-

dition to source or destination synchronized trans-

fers are provided

The interrupt controller provides full programmability

of 248 interrupt sources into 32 priority levels with a

typical interrupt task switch (‘‘latency’’) time of

750 ns

271328 – 2

Figure 2 80960CF Block Diagram

80960CF-30 Datasheet(PDF) 5 Page - Intel Corporation

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