80960CF-30 datasheet(10/62 Pages) INTEL

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SPECIAL ENVIRONMENT 80960CF-30 -25 -16

Table 2 80960CF Pin DescriptionExternal Bus Signals

(Continued)

Name

Type

Description

BTERM

BURST TERMINATE

The burst terminate signal breaks up a burst access and

causes another address cycle to occur The BTERM signal works in conjunction

S(L)

with the internally programmed wait-state generator If READY and BTERM are

H(Z)

enabled in a region the BTERM pin is sampled after the programmed number of

R(Z)

wait states has expired When BTERM is asserted a new ADS signal is generated

and the access is completed The READY input is ignored when BTERM is

asserted BTERM must be externally synchronized to satisfy the BTERM setup

and hold times

WAIT

indicates internal wait state generator status WAIT is asserted when wait

states are being caused by the internal wait state generator and not by the

READY or BTERM inputs WAIT can be used to derive a write-data strobe WAIT

H(Z)

can also be thought of as a READY output that the processor provides when it is

R(1)

inserting wait states

BLAST

BURST LAST

indicates the last transfer in a bus access BLAST is asserted in the

last data transfer of burst and non-burst accesses after the wait state counter

reaches zero BLAST remains asserted until the clock following the last cycle of

H(Z)

the last data transfer of a bus access If the READY or BTERM input is used to

R(0)

extend wait states the BLAST signal remains asserted until READY or BTERM

terminates the access

DTR

DATA TRANSMITRECEIVE

indicates direction for data transceivers DTR is

used in conjunction with DEN to provide control for data transceivers attached to

the external bus When DTR is asserted the signal indicates that the processor

H(Z)

receives data Conversely when deasserted the processor sends data DTR

R(0)

changes only while DEN is high

DEN

DATA ENABLE

indicates data cycles in a bus request DEN is asserted at the

start of the bus request first data cycle and is deasserted at the end of the last

data cycle DEN is used in conjunction with DTR to provide control for data

H(Z)

transceivers attached to the external bus DEN remains asserted for sequential

R(1)

reads from pipelined memory regions DEN is deasserted when DTR changes

LOCK

BUS LOCK

indicates that an atomic read-modify-write operation is in progress

LOCK may be used to prevent external agents from accessing memory which is

currently involved in an atomic operation LOCK is asserted in the first clock of an

H(Z)

atomic operation and deasserted in the clock cycle following the last bus access

R(1)

for the atomic operation To allow the most flexibility for a memory system

enforcement of locked accesses the processor acknowledges a bus hold request

when LOCK is asserted The processor performs DMA transfers while LOCK is

active

HOLD

HOLD REQUEST

signals that an external agent requests access to the external

bus The processor asserts HOLDA after completing the current bus request

S(L)

HOLD HOLDA and BREQ are used together to arbitrate access to the

H(Z)

processor’s external bus by external bus agents

R(Z)

BOFF

BUS BACKOFF

The backoff pin when asserted suspends the current access

and causes the bus pins to float When deasserted the ADS signal is asserted on

S(L)

the next clock cycle and the access is resumed

H(Z)

R(Z)

80960CF-30 Datasheet(PDF) 10 Page - Intel Corporation

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