STC5455 datasheet(17/56 Pages) CONNOR-WINFIELD

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Page 17 of 56 TM121 Rev: P1.3

Date: October 24, 2011

STC5455

Synchronous Clock for SETS

Functional Specification

Data sheet

Preliminary

Detailed Description

The STC5455 is a single chip solution for the syn-

chronous clock in SDH (SETS), SONET, and Syn-

chronous Ethernet network elements. The revolution-

ary pure-digital internal modules, DSP-based PLL

and clock synthesizer are used in the device so that

the overall characteristics are more stable compared

to ones in traditional method.

Chip Master Clock

The STC5455 operates with an external oscillator

(e.g., OCXO or TCXO) as its master clock on the pin

MCLK. Generally, user should select an oscillator has

great stability and low phase noise as the master

clock (MCLK).

The device supports four different accepted frequen-

cies of master clock: 10MHz, 12.8MHz, 19.2MHz,

and 20MHz. Initial default accepted frequency of

MCLK for STC5455 is 12.8MHz. When 10MHz,

19.2MHz, or 20MHz is selected as the frequency of

MCLK, the user must write register MCLK Freq

Reset three times consecutively, with no intervening

read/writes from/to other register. An internal soft-

reset will occur after three writes completed. The

accepted frequency of MCLK input returns to

12.8MHz following any regular reset. See register

MCLK Freq Reset for details.

In the meantime, the STC5455 allows user to read

three values at the register MCLK Freq Reset:

FRQID, COUNT, and ID Written Value.

FRQID

Indicates the ID of the frequency of MCLK that the

STC5455 currently accept.

COUNT

Indicates how many times the register MCLK Freq

Reset has been written to.

ID Written Value

Indicates the ID of associated value that is being writ-

ten to the register MCLK Freq Reset.

See the register MCLK Freq Reset for more details.

Freerun Clock

The STC5455 has an internal freerun clock synthe-

sized from the MCLK. The frequency offset of the

internal freerun clock can be calibrated by writing to

the register Freerun Cali. It has the stability of the

external TCXO/OCXO. The calibration offset may be

programmed

0.1ppm

steps

from

-102.4

+102.3ppm, in 2’s complement. This feature allow the

user can digitally calibrate the freerun clock without

physically adjusting the local oscillator.

Operation Mode

The STC5455 includes two timing generators, T0 and

T4 timing generators. Each timing generator has its

own PLL and can be individually operate in either

external-timing or self-timing mode. In external timing

mode, PLL of a timing generator phase-locks to a ref-

erence input. In self-timing mode, PLL simply oper-

ates

with

the

external

oscillator

(MCLK).

The

STC5455 supports four operation modes: freerun

(self-timing), synchronized (external-timing), pseudo-

holdover (self-timing) and holdover (self-timing).

Freerun Mode

Freerun mode is typically used during system’s initial-

ization stage when none of reference inputs is avail-

able and the clock synchronization has not been

achieved. The clock output generated from the

STC5455 in freerun mode is relative to the internal

freerun clock which is synthesized from MCLK. Fre-

quency of the internal freerun clock can be calibrated

by writing to the register Freerun Cali.

Synchronized Mode

In synchronized mode, the built-in PLL of the timing

generator locks to the selected reference input. Each

timing generator’s loop bandwidth is independently

programmable from 0.1Hz to 100Hz by writing to the

tion of the PLL is determined according to the loop

bandwidth and has maximum gain under 0.2dB. In

synchronized mode, the phase relationship between

the reference input and the clock output can be con-

figured as arbitrary or aligned for timing generator T0

at register Frame Phase Align. Timing generator T4

operates only in phase arbitrary mode.

Pseudo-Holdover Mode

In pseudo-holdover mode, the clock is synthesized

from the MCLK and an accumulated short-term his-

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