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STC5455 Datasheet(PDF) 40 Page - Connor-Winfield Corporation

Part # STC5455
Description  Synchronous Clock for SETS
PDF  56 Pages
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Manufacturer  CONNOR-WINFIELD [Connor-Winfield Corporation]
Direct Link  http://www.conwin.com
Logo CONNOR-WINFIELD - Connor-Winfield Corporation

STC5455 Datasheet(HTML) 40 Page - Connor-Winfield Corporation

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Page 40 of 56 TM121
Rev:P1.3
Date: October 24, 2011
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
STC5455
Synchronous Clock for SETS
Data sheet
Preliminary
1 = Flush/clear both long term history and the device holdover history to 0.
PLL_Event_Out, 0x3E (R/W)
Event0: Reserved
Event1: Reserved
Event2: Reserved
Event3: Reserved
Event4: Reserved
Event5: Reserved
Event6: Reserved
Event7: Reserved
Events are cleared by writing “1” to the bit positions
Default value: 0
PLL_Event_In, 0x3F (R/W)
Writing 1 to trigger the event. If the event is acknowledged by the STC5455, event bit is cleared to be 0.
Event0: Relock:
PLL relocks the selected reference input. If the device operates in phase-align mode, PLL reselects
the frame edge, relocks and frame phase align to the reference input. If the device operates in non
phase-align mode, PLL relocks to the reference input and start over phase rebuild process.
Event1: Reserved
Event2: Reserved
Event3: Reserved
Event4: Reserved
Event5: Reserved
Event6: Reserved
Event7: Reserved
Default value: 0
EX_SYNC_Edge_Config, 0x40 (R/W)
Selects sampling edge (falling or rising) of the external frame sync inputs EX_SYNC1, EX_SYNC2, or
EX_SYNC3.
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x3E
Event7
Event6
Event5
Event4
Event3
Event2
Event1
Event0
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x3F
Not used
Relock
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x40
Not Used
EX_SYNC3
edge
EX_SYNC2
edge
EX_SYCN1
edge



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