STC5455 datasheet(22/56 Pages) CONNOR-WINFIELD

22 / 56 page

Page 22 of 56 TM121 Rev: P1.3

Date: October 24, 2011

STC5455

Synchronous Clock for SETS

Functional Specification

Data sheet

Preliminary

In revertive mode, the automatic reference elector will

pre-empted the current candidate reference if the

new recommended candidate reference has higher

priority.

In non-revertive mode, the current candidate refer-

ence will not be pre-empted by any new candidate

until it is disqualified.

If there is no candidate reference available, freerun or

holdover will be recommended by the automatic ref-

erence elector depending on the holdover history

availability.

Figure 4 shows the operation states for automatic ref-

erence elector.

Figure 4: Automatic Reference Elector States

Automatic Reference Selection

The T0 and T4 timing generators may be individually

operated automatic reference input selection mode.

The mode is selected via the Control Mode registers.

In automatic reference selection mode, the selected

reference is the same reference elected by the auto-

matic reference elector. The automatically selected

reference for each PLL may be read from the Auto

Select Ref registers.

Manual Reference Selection Mode

In manual reference selection mode, the user may

select the reference manually. This mode is selected

via the Control Mode registers. The reference is

Elect

Freerun

Elect

Holdover

Candidate

No Candidate

Reference

Candidate

Reference

Available and

Elect

HO not Available

Reference

Available

Candidate

Available

Reference

No Candidate

Reference

Available and

HO is Available

selected by writing to the Manual Select Ref regis-

ters. The user may also has the device enter freerun

or holdover manually by writing to the Manual Select

Ref registers. Besides, T4 may select T0’s output as

the selected reference.

Hard-wired Manual Reference Selection

Besides the manual reference selection mode, the

STC5455 provides a special mode to switch between

two pre-selected reference directly from a dedicated

pin SRCSW. The two pre-selected references are

configured at the register Hard-wired Switch Pre

Selection. It can make the device enter the freerun or

holdover by writing to the register Hard-wired Switch

Pre Selection. In this mode, the pin SRCSW oper-

ates as a simple switch by setting high or low. Hard-

wired Manual Reference Selection is for T0 only.

Clock Outputs Details

The STC5455 generates 1 synchronized differential

(LVPECL or LVDS) clock output: CLK1; 3 LVCMOS

clock outputs: CLK2, one 8kHz and one 2kHz frame

pulse clock outputs. Figure 5, Figure 6, and Figure 7

respectively show the clock output section for CLK1,

CLK2, and CLK8K/CLK2K. Each output has individ-

ual clock output section consists of synthesizer and

clock generator. Clock generator of CLK1 has

LVPECL/LVDS driver to produce differential output.

Clock generator of CLK2 includes two muxes and a

LVCMOS signal driver. Clock generator of frame out-

put CLK8K and CLK2K consist of a LVCMOS driver.

Clock Synthesizers

The STC5455 has 4 clock synthesizers, which of 3 is

disciplined by the timing generator T0: synthesizer

G1, G2 and one frame pulse clock synthesizer F; T4

disciplines a clock synthesizer GT4 with frequency

fixed at 2.048MHz. Clock synthesizers G1 and G2

produce frequencies from 1MHz to 156.25MHz, in

1kHz steps. Synthesizer F produce Frame8K and

Frame2K at fixed 8kHz and 2kHz. Phase skew of

these synthesizers (except synthesizer GT4) are all

programmable individually up and down 50ns. CLK1

is derived from synthesizer G1. CLK2 can be derived

from synthesizer G2, also can be derived from syn-

thesizer GT4 and F. Synthesizer F produces frame

pulse clock Frame8K and Frame2K which can pro-

gram pulse width at the register Frame8K Sel and

Frame2K Sel.

STC5455 Datasheet(PDF) 22 Page - Connor-Winfield Corporation

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