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STC5455 Datasheet(PDF) 19 Page - Connor-Winfield Corporation

Part # STC5455
Description  Synchronous Clock for SETS
PDF  56 Pages
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Manufacturer  CONNOR-WINFIELD [Connor-Winfield Corporation]
Direct Link  http://www.conwin.com
Logo CONNOR-WINFIELD - Connor-Winfield Corporation

STC5455 Datasheet(HTML) 19 Page - Connor-Winfield Corporation

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Page 19 of 56 TM121 Rev: P1.3
Date: October 24, 2011
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
STC5455
Synchronous Clock for SETS
Functional Specification
Data sheet
Preliminary
Short_Term_Accu_History.
Typically,
short-term
history is used by clock synthesizer in two conditions:
First, it is used in between the transition of two differ-
ent operation modes; second, it is used if LOS occurs
when the STC5455 operates in synchronized mode
with manually reference selection.In addition, short-
term history is provided to perform failure diagnostics
and evaluations.
Long-Term History
Long-term history is an average frequency offset
between the clock output and MCLK which is filtered
internally using a weighted 3rd order low-pass filter
with the long time constant. The -3 dB filter response
point can be programmed from 0.15mHz to 1.3Hz by
writing to the register History Ramp. The history
value can be read from the register Long Term Accu
History.
Device Holdover History
Device holdover history is the history data used when
the STC5455 runs in holdover mode. It is acquired
from the long term history previously described. In
synchronized mode, when timing generators PLL has
locked to the selected reference input for over 15
minutes, the long term history is stored and further
updated as the device holdover history. If LOS or LOL
occurs, the device holdover history will stay at the lat-
est updated value until re-enter the synchronized
mode and the PLL locks to the replaced selected ref-
erence input for another 15 minutes. Set Bit
HO_Usage bit of the register Control Mode to select
using device holdover history. Its value can be read
from the register Device Holdover History.
User-Specified History
The STC5455 allows user to provide the history data
created from their own sophisticated history accumu-
lation algorithms by writing to the register User Spec-
ified History. Set bit HO_Usage of the register Con-
trol Mode to select using user specified holdover his-
tory. Its value can be read from the register User
Specified History.
Phase-Locked Loop Status Details
The register PLL Status contains the detailed status
of the PLLs, including the signal activity of the
selected reference, the synchronization status, and
the availability of the holdover histories.
SYNC bit
In
external-timing
mode, this
bit
indicates
the
achievement of synchronization. This bit will not be
asserted in self-timing mode.
LOS bit
In external-timing mode, this bit indicates the loss of
signal on the selected reference. This bit will not be
asserted in self-timing mode.
LOL bit
In external-timing mode, the bit will be set if the PLL
fails to achieve or maintain lock to the selected refer-
ence. This bit will not be asserted in self-timing mode.
It is also not complementary to the SYNC bit. Both
bits will not be asserted when the PLL is in the pull-in
process. The pull-in process usually occur when
switch to a new selected reference or recover from
the LOS/LOL.
OOP bit
This bit indicates that the selected reference is out of
the pull-in range. This is meaningful only if in exter-
nal-timing mode. This bit will not be asserted in self-
timing mode. The frequency offset is relative to the
digitally calibrated freerun clock.
SAP bit
This bit when set indicates that the PLL’s output
clocks have stopped following the selected reference
because the frequency offset of the selected refer-
ence is out of pull-in range (OOP). User can write to
the Control Mode register to program whether the
PLL shall follow the selected reference outside of the
specified pull-in range or just stay within the pull-in
range boundary.
FEE bit
This bit indicates whether an error occurs in the frame
edge detection process in phase align mode.
DHT bit
This bit indicates whether the device holdover history
is tracking on the current selected reference (updat-
ing by the long-term history).
HHA bit
This bit indicates the availability of the holdover his-
tory, which may be either the user provided history or
the device holdover history.



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