STC5455 datasheet(54/56 Pages) CONNOR-WINFIELD

54 / 56 page

Page 54 of 56 TM121

Rev:P1.3

Date: October 24, 2011

STC5455

Synchronous Clock for SETS

Data sheet

Preliminary

Revision History

The following table summarizes significant changes made in each revision. Additions reference current pages.

Revision

Change Description

Pages

Initial datasheet at Preliminary status

P1.1

Add mechanical specifications

P1.2

Correct SDI of SPI Bus Timing, Write access

P1.3

Update Functional diagram

Remove LVCMOS level for REF4 and REF5

1, 6, 14, 20,

Add register Frame_Mux

9, 45

Change register CLK8K_Sel and CLK2K_Sel to Frame8K_Sel and

CLK2K_Sel

9, 44

Change name of register Ref_Freq to Ref_Acceptable_Freq

11, 20, 31, 44,

Add description of frame mux

Update CLK3~CLK8, CLK8K and CLK2K detail diagram in Figure 6, 7

Correct tCH and tCL, LSB to MSB and MSB to LSB in serial bus timing figure

26, 27

Correct Min value of tCH and tCL to 50ns in serial bus timing table

Correct description of tCSHLD and tCSTRI in serial bus timing table

Update register description of Bucket_Size, Ref_Info, Interrupt_Event_Sts,

PLL_Event_Out, PLL_Event_In, CLK2_Sel, Synth_Index_Select,

Synth_Freq_Value, Synth_Skew_Adj, Control_Mode

29, 31, 32, 39, 40, 41, 42, 43,

Correct default value of register Frame8K_Sel and Frame2K_Sel

Update order information

Add section of Specification Modification

Change synthesizer G4 to G2

All pages

Miscellaneous

All pages

STC5455 Datasheet(PDF) 54 Page - Connor-Winfield Corporation

STC5455 Datasheet(HTML) 54 Page - Connor-Winfield Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datasheet Download

Link URL