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STC5455 Datasheet(PDF) 26 Page - Connor-Winfield Corporation |
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STC5455 Datasheet(HTML) 26 Page - Connor-Winfield Corporation |
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26 / 56 page ![]() Page 26 of 56 TM121 Rev:P1.3 Date: October 24, 2011 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice STC5455 Synchronous Clock for SETS Data sheet Preliminary Processor Interface Descriptions The STC5455 supports SPI bus interface: The SPI interface bus mode uses the CS, SCLK,SDI, SDO pins, with timing as shown in Figure 8, Figure 9 and Figure 10. For read operation, serial data output can be read out from the STC5455 on either the rising or fall- ing edge of the SCLK. The edge selection depends on pin CLKE logic level. Serial Bus Timing Figure 8:SPI Bus, Read access (Pin CLKE = Low) Figure 9: SPI Bus Timing, Read access (Pin CLKE = High) A0 CS SCLK SDI 1 2 3 4 A5 A4 A3 A2 A1 5 6 7 8 13 14 15 16 9 10 11 12 A6 D7 MSB LSB SDO LSB MSB tDRDY tCL tCH tCS tDs tDh tCSMIN tDHLD D6 D5 D4 D3 D2 D1 D0 tCSHLD tCSTRI 1 A0 CS SCLK SDI 1 2 3 4 A6 A5 A4 A3 A2 A1 5 6 7 8 13 14 15 16 9 10 11 12 1 D7 MSB LSB SDO LSB MSB tDRDY tCL tCH tCS tDs tDh tCSMIN tDHLD D6 D5 D4 D3 D2 D1 D0 tCSHLD tCSTRI |
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