STC5455 datasheet(23/56 Pages) CONNOR-WINFIELD

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Page 23 of 56 TM121 Rev: P1.3

Date: October 24, 2011

STC5455

Synchronous Clock for SETS

Functional Specification

Data sheet

Preliminary

Clock Generators

Clock generator of CLK1 consists of a LVPECL/LVDS

signal driver. The signal level of clock outputs CLK1

can be programmed to either LVPECL or LVDS at the

Clock generator of CLK2 consists of a Frame mux,

CLK2 Sel Mux, and a LVCMOS driver. CLK2 Sel Mux

determines which synthesizer is selected for T0 gen-

erator to output CLK2. When synthesizer F is

selected, Frame Mux selects one of frame clocks

(Frame8K or Frame2K) derived from synthesizer F

and forward it to CLK2 Sel Mux for frame signal

selection of CLK2. Frame Mux is set at the register

Frame Mux and the CLK2 Sel Mux is set at the regis-

ter CLK2 Sel for CLK2. Signal level is driven from

LVCMOS driver in CLK2 generator.

The clock generator of CLK8K and CLK2K contains a

LVCMOS driver. Clock outputs CLK8K and CLK2K

output Frame8K and Frame2K clock pulse clock. The

duty cycle is programmable at the register Frame8K

Sel and Frame2K Sel.

Figure 5:Output Clocks CLK1

Figure 6:Output Clocks CLK2

Figure 7:Output Clocks CLK8K and CLK2K

Clock Output Phase Alignment

Any of clock outputs (except the one derived from

CLK1

Synthesizer G1

CLK1 Generator

LVPECL

/LVDS

DRIVER

1MHz ~ 156.25MHz

CLK2 Generator

LVCMOS

DRIVER

Synthesizer G2

Synthesizer GT4

CLK2

1MHz ~ 156.25MHz

Synth

Frame8K

Frame2K

Frame

Mux

CLK2

Sel

2.048MHz

Synthesizer F

LVCMOS

Driver

CLK8K

CLK8K Generator

LVCMOS

Driver

CLK2K

CLK2K Generator

8kHz frame pulse

2kHz frame pulse

Frame8K

Duty Cycle

Control

Frame2K

Duty Cycle

Control

synthesizer GT4) which has frequency at the integer

multiple of 8kHz is in phase alignment with the frame

pulse output CLK8K if none of synthesizer skew is

programmed.

Synthesizer Skew Programming

The STC5455 allows user to program the phase skew

of each clock synthesizer except synthesizer GT4, up

and down 50ns in roughly 0.024ns steps. Since each

of clock outputs is dedicate derived from its synthe-

sizer respectively, adjust phase skew of the synthe-

sizer will provide the associated clock output a phase

skew adjustment. Any clock output derived from syn-

thesizer GT4 is not phase skew programmable

because of phase skew of synthesizer GT4 is fixed at

0. Phase skew of the synthesizer G1, G2, and F may

be programmed at the register Synth Index Select

and Synth Skew Adj.

Clock Outputs

CLK1 is selected at the register CLK1 Sel. Output

frequency or phase skew of CLK1 is programmable

when frequency or phase skew of synthesizer G1 is

programmed at the register Sync Index Select,

Synth Freq Value, and Synth Skew Adj. Output fre-

quency is programmable from 1MHz to 156.25MHz,

in 1kHz steps.

CLK2 is selected when synthesizer G2, GT4, or F is

selected at the register CLK2 Sel. Output frequency

or phase skew of CLK2 is programmable when fre-

quency or phase skew of synthesizer G2 is program-

mable at the register Synth Index Select, Synth

Freq Value, and Synth Skew Adj. Output frequency

of CLK2 is programmable from 1MHz to 156.25MHz,

in 1kHz steps, via either synthesizer G2 or GT4 indi-

vidually. CLK2 can also output frame pulse clock

Frame8K or Frame2K of synthesizer F. Frame8K or

Frame2K is selected at the register Frame Mux for

CLK2 selection. Phase skew of frame pulse clocks is

programmable simultaneously at the register Synth

Index Select and Synth Skew Adj.

CLK8K and CLK2K derived from synthesizer F output

Frame8K and Frame2K clock pulse clock.

Redundant Application

Timing generator T0 supports multiple-master opera-

tion for redundant applications to allow system

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